SRAM_CTRL/MAIN Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.772m	18.640ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.110s	23.504us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	27.152us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.610s	201.516us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.140s	23.399us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.730s	360.744us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	27.152us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	23.399us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.698m	57.920ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.664m	4.926ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	25.176m	47.175ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.942m	24.775ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	52.576m	982.040ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.192m	21.820ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.667m	59.515ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.608m	30.227ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.931m	5.170ms	50	50	100.00
		sram_ctrl_partial_access_b2b	16.267m	123.589ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.787m	3.178ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.802m	3.126ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.990m	59.196ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.330s	1.778ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.706h	2.212s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.140s	15.470us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.720s	482.158us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.720s	482.158us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.110s	23.504us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	27.152us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	23.399us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	117.320us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.110s	23.504us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	27.152us	20	20	100.00
		sram_ctrl_csr_aliasing	1.140s	23.399us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	117.320us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.327m	7.214ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
		sram_ctrl_tl_intg_err	7.090s	9.554ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	7.090s	9.554ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.990m	59.196ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	27.152us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.608m	30.227ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.608m	30.227ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.608m	30.227ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.667m	59.515ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.327m	7.214ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.772m	18.640ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.772m	18.640ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.772m	18.640ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.608m	30.227ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.667m	59.515ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.772m	18.640ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.240s	1.618ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.507m	35.602ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1040	1040	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.92	99.17	94.27	99.72	100.00	95.89	99.13	97.26

Past Results

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• 2024.09.10_08.14.52
• 2024.09.05_04.24.31
• 2024.09.02_11.34.09
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