SRAM_CTRL/MAIN Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.100m	5.708ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.150s	31.063us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	15.622us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.440s	346.314us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.170s	35.125us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	10.710s	5.777ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	15.622us	20	20	100.00
		sram_ctrl_csr_aliasing	1.170s	35.125us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.240m	82.728ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.575m	19.204ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.363m	10.781ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.195m	5.407ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	53.096m	948.257ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	26.898m	147.287ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.303m	58.729ms	50	50	100.00
V2	executable	sram_ctrl_executable	30.078m	112.050ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.824m	17.955ms	50	50	100.00
		sram_ctrl_partial_access_b2b	13.583m	120.179ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.048m	3.182ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.861m	827.823us	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.346m	13.525ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	9.860s	6.723ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.482h	4.681s	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	1.130s	21.073us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.530s	57.032us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.530s	57.032us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.150s	31.063us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	15.622us	20	20	100.00
		sram_ctrl_csr_aliasing	1.170s	35.125us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	23.407us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.150s	31.063us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	15.622us	20	20	100.00
		sram_ctrl_csr_aliasing	1.170s	35.125us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	23.407us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.605m	7.330ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
		sram_ctrl_tl_intg_err	4.040s	932.307us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.040s	932.307us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.346m	13.525ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.346m	13.525ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	15.622us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	30.078m	112.050ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	30.078m	112.050ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	30.078m	112.050ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.303m	58.729ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.605m	7.330ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.610s	2.995ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.100m	5.708ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.100m	5.708ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	30.078m	112.050ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.303m	58.729ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.100m	5.708ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.370s	356.763us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.138m	17.653ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1087	1090	99.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	15	93.75
V2S	4	4	3	75.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.59	99.50	96.05	99.72	100.00	97.34	99.13	98.35

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 3.sram_ctrl_stress_all.3202433084833454181399262983979865346049296413708849059782320898904675542642
      Log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

    • 15.sram_ctrl_passthru_mem_tl_intg_err.71745373139519487127869975077048814582596570632288943776455523581276852551975
      Line 132, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/15.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

        UVM_ERROR @ 2350926000 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2350926000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 45.sram_ctrl_stress_all.84128994140191969668403521356398680693320039657279694971129543355001412174420
      Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_main-sim-vcs/45.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 4102649471191 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x169eb1b8
        UVM_INFO @ 4102649471191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.10_10.18.58
• 2024.10.04_00.45.49
• 2024.09.25_11.04.52
• 2024.09.19_09.08.30
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