SRAM_CTRL/MAIN Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.647m	1.431ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.260s	50.097us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.070s	14.895us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.660s	185.274us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.110s	20.572us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	9.070s	2.906ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.070s	14.895us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	20.572us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.985m	20.712ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.905m	115.873ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.752m	189.994ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.321m	7.041ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	49.671m	158.983ms	49	50	98.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.689m	18.992ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.997m	86.411ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.459m	22.922ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.270m	6.300ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.337m	7.831ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.071m	794.346us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.023m	1.599ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.068m	20.748ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.640s	2.393ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.081h	334.756ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.130s	49.607us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.670s	120.508us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.670s	120.508us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.260s	50.097us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	14.895us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	20.572us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.330s	45.766us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.260s	50.097us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	14.895us	20	20	100.00
		sram_ctrl_csr_aliasing	1.110s	20.572us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.330s	45.766us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.831m	141.184ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
		sram_ctrl_tl_intg_err	4.660s	4.718ms	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.660s	4.718ms	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.068m	20.748ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.070s	14.895us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.459m	22.922ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.459m	22.922ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.459m	22.922ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.997m	86.411ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.831m	141.184ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.647m	1.431ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.647m	1.431ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.647m	1.431ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.459m	22.922ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.997m	86.411ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.647m	1.431ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.820s	437.365us	5	5	100.00
V2S		TOTAL			43	45	95.56
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.484m	3.141ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	1	33.33
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.97	99.19	94.27	99.72	100.00	96.03	99.12	97.44

Failure Buckets

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.

4.sram_ctrl_passthru_mem_tl_intg_err.30437168312125892425865118373733596140855752085405564965362187966755518684727
Line 202, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_ERROR @ 11639109160 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 11639109160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sram_ctrl_tl_intg_err has 1 failures.

7.sram_ctrl_tl_intg_err.65187535676919215171511038880991869909867124383117196618357924654081605433039
Line 169, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/7.sram_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @  41572306 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @  41572306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 2.sram_ctrl_executable.62345505113524288056410277189294892645204791315277599487975106111573323621578
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/2.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 21033421715 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x6d5b868e
  UVM_INFO @ 21033421715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 15.sram_ctrl_stress_all.35621821020928796877148860447592165729081053045349364320203749247830094223791
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 127720660089 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xd40089c8
  UVM_INFO @ 127720660089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test sram_ctrl_bijection has 1 failures.
  - 36.sram_ctrl_bijection.61901355790419056341700281209321385545594858093152301414937236868703647230634
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```