SRAM_CTRL/MAIN Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.435m	808.947us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.190s	40.170us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.100s	38.897us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	4.030s	867.422us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.160s	50.718us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	8.000s	2.823ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.100s	38.897us	20	20	100.00
		sram_ctrl_csr_aliasing	1.160s	50.718us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.096m	82.799ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.551m	20.792ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.765m	18.568ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.309m	10.842ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	44.944m	140.267ms	48	50	96.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.326m	82.172ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.631m	75.244ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.203m	122.196ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.189m	1.371ms	50	50	100.00
		sram_ctrl_partial_access_b2b	13.588m	103.662ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.021m	7.645ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.943m	1.572ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.830m	20.779ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	8.040s	4.179ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.715h	483.620ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.160s	18.547us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.150s	168.606us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.150s	168.606us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.190s	40.170us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	38.897us	20	20	100.00
		sram_ctrl_csr_aliasing	1.160s	50.718us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.350s	45.916us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.190s	40.170us	5	5	100.00
		sram_ctrl_csr_rw	1.100s	38.897us	20	20	100.00
		sram_ctrl_csr_aliasing	1.160s	50.718us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.350s	45.916us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.582m	11.605ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
		sram_ctrl_tl_intg_err	4.630s	684.679us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.630s	684.679us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.830m	20.779ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.830m	20.779ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.100s	38.897us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.203m	122.196ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.203m	122.196ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.203m	122.196ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.631m	75.244ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.582m	11.605ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.435m	808.947us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.435m	808.947us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.435m	808.947us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.203m	122.196ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.631m	75.244ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.435m	808.947us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.440s	931.253us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.351m	4.919ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1035	1040	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.30	99.25	95.11	99.72	100.00	96.38	99.13	98.54

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test sram_ctrl_bijection has 2 failures.

    • 1.sram_ctrl_bijection.107928006334568059825702926712256201475036352353032503537994080536500307601558
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/1.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.sram_ctrl_bijection.12593674422584183513358184931166267055247073113564708571476934481249691981276
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/36.sram_ctrl_bijection/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 30.sram_ctrl_stress_all.58078662261125950350420419818384656611024384353366238797159306215346447506890
      Line 148, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/30.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 192104969119 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x74a8d0ca
        UVM_INFO @ 192104969119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sram_ctrl_executable has 1 failures.

    • 42.sram_ctrl_executable.54302450080748306388212444526058130243486865062429679335887590494021539498087
      Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/42.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 46192359941 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7e502de5
        UVM_INFO @ 46192359941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 47.sram_ctrl_multiple_keys.30841358392994961771793883420908390207979745520825794596122910449253571521276
      Line 99, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_main-sim-vcs/47.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 80358941779 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x727ffe48
        UVM_INFO @ 80358941779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.09.25_11.04.52
• 2024.09.19_09.08.30
• 2024.09.12_10.20.09
• 2024.09.10_08.14.52
• 2024.09.05_04.24.31
• 2024.09.02_11.34.09
• 2024.08.29_23.16.15