SRAM_CTRL/RET Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: e3fb01b5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.818m	2.732ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.650s	17.027us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.890s	26.913us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.920s	190.324us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	46.163us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.660s	33.586us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.890s	26.913us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	46.163us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.490s	1.301ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.840s	1.785ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	27.013m	3.747ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.670m	9.266ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.320m	21.747ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.852m	22.425ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	18.630s	670.736us	50	50	100.00
V2	executable	sram_ctrl_executable	31.511m	59.131ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.431m	3.677ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.673m	93.665ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.944m	670.822us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.305m	157.678us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.957m	25.093ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.350s	41.246us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.608h	262.027ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.800s	25.982us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.190s	126.923us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.190s	126.923us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.650s	17.027us	5	5	100.00
		sram_ctrl_csr_rw	0.890s	26.913us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	46.163us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.980s	20.589us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.650s	17.027us	5	5	100.00
		sram_ctrl_csr_rw	0.890s	26.913us	20	20	100.00
		sram_ctrl_csr_aliasing	0.700s	46.163us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.980s	20.589us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	10.070s	388.596us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
		sram_ctrl_tl_intg_err	2.570s	633.001us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.570s	633.001us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.957m	25.093ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.890s	26.913us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.511m	59.131ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.511m	59.131ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.511m	59.131ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	18.630s	670.736us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	10.070s	388.596us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.818m	2.732ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.818m	2.732ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.511m	59.131ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	18.630s	670.736us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.818m	2.732ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.050s	854.073us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.905h	1.093ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1036	1040	99.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.26	99.16	93.54	100.00	70.00	97.41	99.70	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 18.sram_ctrl_stress_all.1804566732
      Line 251, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 40149820000 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x129329ae
        UVM_INFO @ 40149820000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test sram_ctrl_regwen has 1 failures.

    • 19.sram_ctrl_regwen.630124411
      Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_regwen/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 37.sram_ctrl_multiple_keys.4208823854
      Line 247, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 38305497584 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xdaa79a9e
        UVM_INFO @ 38305497584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 45.sram_ctrl_stress_all.3856658768
      Line 254, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 66244752456 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xbcbb34c
        UVM_INFO @ 66244752456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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