042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 1.573m | 2.635ms | 44 | 50 | 88.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.630s | 77.505us | 3 | 5 | 60.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.680s | 13.972us | 13 | 20 | 65.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.880s | 152.760us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.720s | 37.165us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 3.230s | 541.109us | 16 | 20 | 80.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.680s | 13.972us | 13 | 20 | 65.00 |
| sram_ctrl_csr_aliasing | 0.720s | 37.165us | 4 | 5 | 80.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 12.250s | 8.122ms | 38 | 50 | 76.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.240s | 158.665us | 34 | 50 | 68.00 |
| V1 | TOTAL | 157 | 205 | 76.59 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 30.231m | 52.906ms | 42 | 50 | 84.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.063m | 4.011ms | 42 | 50 | 84.00 |
| V2 | bijection | sram_ctrl_bijection | 1.445m | 63.550ms | 42 | 50 | 84.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 22.972m | 3.862ms | 40 | 50 | 80.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 17.360s | 705.953us | 38 | 50 | 76.00 |
| V2 | executable | sram_ctrl_executable | 24.296m | 16.921ms | 41 | 50 | 82.00 |
| V2 | partial_access | sram_ctrl_partial_access | 1.595m | 201.185us | 39 | 50 | 78.00 |
| sram_ctrl_partial_access_b2b | 7.250m | 75.320ms | 37 | 50 | 74.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 1.656m | 1.364ms | 39 | 50 | 78.00 |
| sram_ctrl_throughput_w_partial_write | 1.868m | 210.380us | 41 | 50 | 82.00 | ||
| V2 | regwen | sram_ctrl_regwen | 22.862m | 3.436ms | 40 | 50 | 80.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 1.690s | 49.065us | 36 | 50 | 72.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.389h | 32.128ms | 33 | 50 | 66.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.710s | 27.262us | 40 | 50 | 80.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.210s | 297.446us | 16 | 20 | 80.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.210s | 297.446us | 16 | 20 | 80.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.630s | 77.505us | 3 | 5 | 60.00 |
| sram_ctrl_csr_rw | 0.680s | 13.972us | 13 | 20 | 65.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 37.165us | 4 | 5 | 80.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 49.978us | 13 | 20 | 65.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.630s | 77.505us | 3 | 5 | 60.00 |
| sram_ctrl_csr_rw | 0.680s | 13.972us | 13 | 20 | 65.00 | ||
| sram_ctrl_csr_aliasing | 0.720s | 37.165us | 4 | 5 | 80.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 49.978us | 13 | 20 | 65.00 | ||
| V2 | TOTAL | 579 | 740 | 78.24 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 10.300s | 1.795ms | 16 | 20 | 80.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| sram_ctrl_tl_intg_err | 2.300s | 866.890us | 16 | 20 | 80.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.300s | 866.890us | 16 | 20 | 80.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 22.862m | 3.436ms | 40 | 50 | 80.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.680s | 13.972us | 13 | 20 | 65.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 24.296m | 16.921ms | 41 | 50 | 82.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 24.296m | 16.921ms | 41 | 50 | 82.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 24.296m | 16.921ms | 41 | 50 | 82.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 17.360s | 705.953us | 38 | 50 | 76.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 10.300s | 1.795ms | 16 | 20 | 80.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 1.573m | 2.635ms | 44 | 50 | 88.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 1.573m | 2.635ms | 44 | 50 | 88.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 24.296m | 16.921ms | 41 | 50 | 82.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 17.360s | 705.953us | 38 | 50 | 76.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 1.573m | 2.635ms | 44 | 50 | 88.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.050s | 353.071us | 3 | 5 | 60.00 |
| V2S | TOTAL | 35 | 45 | 77.78 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 1.744h | 11.400ms | 39 | 50 | 78.00 |
| V3 | TOTAL | 39 | 50 | 78.00 | |||
| TOTAL | 810 | 1040 | 77.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 1 | 12.50 |
| V2 | 16 | 16 | 0 | 0.00 |
| V2S | 3 | 3 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 100.00 | 98.13 | 100.00 | 100.00 | 99.71 | 99.70 | 99.81 |
Exit reason: Error: User command failed Job returned non-zero exit code has 204 failures:
0.sram_ctrl_smoke.21948702659973263248589982158556050602478490382671876779745290910569477805759
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_smoke/latest/run.log
[make]: simulate
cd /workspace/0.sram_ctrl_smoke/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973444799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.973444799
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:47 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.sram_ctrl_smoke.18626775655929147021100353812431615631274276206260279625771168002337968908142
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_smoke/latest/run.log
[make]: simulate
cd /workspace/11.sram_ctrl_smoke/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118360430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3118360430
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:47 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
0.sram_ctrl_multiple_keys.73867922566929513271828862735728521761925852145275083243227162124456687774658
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_multiple_keys/latest/run.log
[make]: simulate
cd /workspace/0.sram_ctrl_multiple_keys/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80948162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multiple_keys.80948162
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
17.sram_ctrl_multiple_keys.81534900487106555349415589407446716693893892902491116676389180374305082041850
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_multiple_keys/latest/run.log
[make]: simulate
cd /workspace/17.sram_ctrl_multiple_keys/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846849530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multiple_keys.846849530
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:47 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
0.sram_ctrl_ram_cfg.60534531780677338602793004392271000301312805080539505101576875260817435956402
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_ram_cfg/latest/run.log
[make]: simulate
cd /workspace/0.sram_ctrl_ram_cfg/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70685874 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.70685874
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.sram_ctrl_ram_cfg.41486554686058495514941367891166990442935788595248871654978905067451028060887
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_ram_cfg/latest/run.log
[make]: simulate
cd /workspace/3.sram_ctrl_ram_cfg/latest && /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886974167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2886974167
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 12 more failures.
0.sram_ctrl_mem_walk.79228265777685711005930078576434286597971337376581101356602829017205306844319
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mem_walk/latest/run.log
[make]: simulate
cd /workspace/0.sram_ctrl_mem_walk/latest && /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349701791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_mem_walk.3349701791
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.sram_ctrl_mem_walk.96083005829016908433483090585986795638685298780132530638308350416740791476789
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mem_walk/latest/run.log
[make]: simulate
cd /workspace/1.sram_ctrl_mem_walk/latest && /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001330741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_mem_walk.2001330741
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:46 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 9 more failures.
0.sram_ctrl_tl_intg_err.112623140258408207226317492372226649984982248057538563671937106406277540382569
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/0.sram_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739149673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_tl_intg_err.739149673
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.sram_ctrl_tl_intg_err.25066187699185394697556258459228643629399983192821516522328167533310868204604
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/1.sram_ctrl_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427989052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_tl_intg_err.2427989052
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:30 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Job sram_ctrl_ret-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
Test sram_ctrl_bijection has 1 failures.
1.sram_ctrl_bijection.12034675421929332915022714641932935361375085672778582655533540314361427587604
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_bijection/latest/run.log
Job ID: smart:3c718955-116c-40ba-9be5-6ce1f00b4ece
Test sram_ctrl_sec_cm has 1 failures.
2.sram_ctrl_sec_cm.65299078045384527246929880320434504028533541312611676116843494847284385579652
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
Job ID: smart:e57b0c88-12e6-46ce-899e-fe4dedee1032
Test sram_ctrl_stress_all has 3 failures.
4.sram_ctrl_stress_all.55313569148129736072627757943027587955504248081774054007679709678818117119132
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
Job ID: smart:77130410-763c-4ea9-9f64-a9a49d0607da
5.sram_ctrl_stress_all.48783803742840969973754528850425021405227002388796799962808100522764919906778
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
Job ID: smart:28b1199e-7bef-4ae4-8c2d-933a5e0a5256
... and 1 more failures.
Test sram_ctrl_mem_walk has 1 failures.
13.sram_ctrl_mem_walk.79959791619809299810539763490645972410563623625823827319160230972299547743630
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mem_walk/latest/run.log
Job ID: smart:7c2b389f-6ab2-42ec-bc25-2124832f3019
Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
23.sram_ctrl_stress_all_with_rand_reset.90564028125801833798145886517239698664301934337591567108821042198524344421223
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4f2f3b30-c647-464b-b7c1-042a67f18f28
... and 3 more tests.
UVM_ERROR (sram_ctrl_scoreboard.sv:369) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 7 failures:
1.sram_ctrl_lc_escalation.37063007220781984844785353916094204744620322101324830104436349825134728983075
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 201652570 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 201652570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.sram_ctrl_lc_escalation.63220992330062867089390554372125720914176964509433669236219453052273072853033
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 205974568 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 205974568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
1.sram_ctrl_stress_all.45885135147718760292260144332888978525204151671455730075633152202260811895137
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 838138591 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 838138591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.sram_ctrl_stress_all.7176499875069309553610512924477752281098566359733070573158023313125627748555
Line 307, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 1620598505 ps: (sram_ctrl_scoreboard.sv:369) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 1620598505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job sram_ctrl_ret-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test sram_ctrl_passthru_mem_tl_intg_err has 2 failures.
4.sram_ctrl_passthru_mem_tl_intg_err.88407846963017768652469431261695448861058263109218400460060332728211816767679
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
Job ID: smart:3a9483c0-fbed-439c-8635-ef1ed2684e9f
7.sram_ctrl_passthru_mem_tl_intg_err.39817803476916235630691284730505056574572276717801482658722712512768481264595
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
Job ID: smart:28a614a6-4607-4eb1-8747-458f52cb73de
Test sram_ctrl_tl_intg_err has 1 failures.
8.sram_ctrl_tl_intg_err.23777945040723294688616227107024817564841877557451685781602662835488921441275
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_tl_intg_err/latest/run.log
Job ID: smart:11ad030b-aa81-42a3-adb1-30e5387d93af
Test sram_ctrl_same_csr_outstanding has 2 failures.
8.sram_ctrl_same_csr_outstanding.113211802663187692864647954221244785752984121707177720559597287177758201804887
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_same_csr_outstanding/latest/run.log
Job ID: smart:7b2bd996-d56f-4841-a2bd-20948a82f339
10.sram_ctrl_same_csr_outstanding.109293816326568868535662408132501831613050566244064763802712491589705458030043
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_same_csr_outstanding/latest/run.log
Job ID: smart:d8d2db33-0f24-4da6-aa4f-05945653a8d1
Test sram_ctrl_csr_rw has 1 failures.
9.sram_ctrl_csr_rw.87826100960301359214826362988199495845629017201447502701207279567495078030125
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_rw/latest/run.log
Job ID: smart:863a8856-26ed-4308-8b7c-b38be5ac41f5
Test sram_ctrl_tl_errors has 1 failures.
11.sram_ctrl_tl_errors.87309691143104408421368540619804881532387806237015847240156676832411340322941
Log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_tl_errors/latest/run.log
Job ID: smart:8b8e4a9b-593c-45e2-8bab-1a8e1b5aa324
UVM_FATAL (cip_base_vseq.sv:245) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
44.sram_ctrl_regwen.62371789299765173577298307623609575947128357726575037024618842295882263590681
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 30209036005 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x28f68afd
UVM_INFO @ 30209036005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---