SRAM_CTRL/RET Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.134m	3.003ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	38.317us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	19.256us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.360s	450.238us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	18.954us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.690s	182.750us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	19.256us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	18.954us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.210s	5.004ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.050s	1.151ms	50	50	100.00
V1		TOTAL			185	205	90.24
V2	multiple_keys	sram_ctrl_multiple_keys	32.919m	59.507ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.034m	16.762ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.397m	3.737ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.179m	3.969ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	16.120s	1.095ms	46	50	92.00
V2	executable	sram_ctrl_executable	41.240m	15.047ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.772m	1.163ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.910m	29.008ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.595m	275.671us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.888m	2.077ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	30.503m	24.426ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.280s	47.676us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.065h	276.197ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.720s	25.988us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.900s	144.639us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.900s	144.639us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	38.317us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	19.256us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	18.954us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	19.546us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	38.317us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	19.256us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	18.954us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	19.546us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	12.230s	423.430us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
		sram_ctrl_tl_intg_err	2.890s	831.423us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.890s	831.423us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	30.503m	24.426ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	19.256us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	41.240m	15.047ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	41.240m	15.047ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	41.240m	15.047ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	16.120s	1.095ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	12.230s	423.430us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.134m	3.003ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.134m	3.003ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	41.240m	15.047ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	16.120s	1.095ms	46	50	92.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.134m	3.003ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.240s	602.176us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.670m	1.362ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			957	1040	92.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	100.00	97.48	100.00	100.00	99.14	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:788) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 50 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.69294007412324749627029331338236569489577570700383680454604026906484332724560
    Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1183858827 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1183858827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.59854459454751875419417402081321197093334761939966335094769450035852445194770
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 252052232 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 252052232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 11 failures:

Test sram_ctrl_lc_escalation has 4 failures.

5.sram_ctrl_lc_escalation.98738002659289820880458603213449258463965179873720840648830064822579586989709
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @  90617449 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @  90617449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.sram_ctrl_lc_escalation.75908741780314251926243094269519914729131540719709097964714072086473295408636
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 449080702 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 449080702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sram_ctrl_stress_all has 7 failures.

15.sram_ctrl_stress_all.64672052531307338659609500859619248380053753140946694211441380787220598599764
Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2508887310 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 2508887310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.sram_ctrl_stress_all.48782829465049152121077369133043785621799746943659483791838742385194055464800
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 15977387975 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 15977387975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 7 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 7 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.97735953505449838942319117339903105650393433293379140837537434207450369448832
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46118645 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  46118645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.109565931325201517811069174754923751329628556760899836449308508363035913923509
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  94075200 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  94075200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 5 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 5 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.92216656243228221896544272021451789077869882322552093646175483427333718265639
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  50084832 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  50084832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.1784197546042940152343684135525729850502899655263094081586767644450986018696
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  87340817 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  87340817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 4 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 4 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.80638429210644614728756384080149179645284968912645159909510100772692534928693
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  52216631 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  52216631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.102829708078503545034291278730267387863546096059647746181272180970206880205921
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27089011 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  27089011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 3 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.44125796501137377356805543339685248615521535048754163057445258148368816579306
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107602666 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 107602666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.9258565280811200523131503981899874598181420976428151603573966059911137750895
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28202175 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  28202175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.105629118319159044599079817753843353090027490717997001821149662461300474598459
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28965018 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  28965018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 22.sram_ctrl_regwen.2412632851661816248291975626812681664952234983880098510806326709803635212306
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 28807043694 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x613ea397
  UVM_INFO @ 28807043694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 27.sram_ctrl_executable.76548007550326790310045909563623383493306510285830857060622012377022771661314
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 25666681499 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xde8b02a
  UVM_INFO @ 25666681499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```