c30684b3ca| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.089m | 1.294ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.740s | 35.542us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.720s | 15.527us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.950s | 277.207us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.760s | 21.671us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.760s | 148.184us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.720s | 15.527us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.760s | 21.671us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 11.620s | 3.836ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.910s | 1.493ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 205 | 205 | 100.00 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 29.120m | 62.525ms | 46 | 50 | 92.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.668m | 8.933ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.287m | 9.976ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 4.010m | 475.337us | 1 | 50 | 2.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 2.871m | 19.504ms | 42 | 50 | 84.00 |
| V2 | executable | sram_ctrl_executable | 27.703m | 33.119ms | 49 | 50 | 98.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.515m | 2.677ms | 48 | 50 | 96.00 |
| sram_ctrl_partial_access_b2b | 8.347m | 38.136ms | 48 | 50 | 96.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.340m | 760.565us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.264m | 168.152us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 28.089m | 98.703ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.840s | 29.734us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.385h | 66.462ms | 35 | 50 | 70.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.750s | 27.061us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 5.480s | 180.692us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 5.480s | 180.692us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.740s | 35.542us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 15.527us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.760s | 21.671us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 84.594us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.740s | 35.542us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 15.527us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.760s | 21.671us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.820s | 84.594us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 658 | 740 | 88.92 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.520s | 2.137ms | 19 | 20 | 95.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 3.070s | 540.847us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 3.070s | 540.847us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 28.089m | 98.703ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.720s | 15.527us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 27.703m | 33.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 27.703m | 33.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 27.703m | 33.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 2.871m | 19.504ms | 42 | 50 | 84.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.520s | 2.137ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.089m | 1.294ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.089m | 1.294ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 27.703m | 33.119ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 2.871m | 19.504ms | 42 | 50 | 84.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.089m | 1.294ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 4.310s | 924.939us | 5 | 5 | 100.00 |
| V2S | TOTAL | 44 | 45 | 97.78 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 12.771m | 12.448ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 950 | 1040 | 91.35 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 16 | 16 | 8 | 50.00 |
| V2S | 3 | 3 | 2 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.44 | 100.00 | 98.18 | 100.00 | 100.00 | 99.71 | 99.70 | 98.52 |
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 49 failures:
0.sram_ctrl_access_during_key_req.82496773592347184544944528681735230619007341655147641969265750074121699059418
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 3726614974 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x0) != exp (0x4a)
UVM_INFO @ 3726614974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_access_during_key_req.27495213304001021318149229082406402227681937236227285113906237076676633761310
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 68886423 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x21) != exp (0x50)
UVM_INFO @ 68886423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:413) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 16 failures:
Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
3.sram_ctrl_stress_all_with_rand_reset.52652044659707706651106628339409217256861361662758065877161841291113171449748
Line 326, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12643308206 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 12643308206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_multiple_keys has 4 failures.
5.sram_ctrl_multiple_keys.78178322987722694566292075009892033758671494860092126654176534189950477603735
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 8820390973 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 8820390973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.sram_ctrl_multiple_keys.22509894814399561330649597454644714298233046862448227426151105299136452034292
Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 33637660381 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 33637660381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
5.sram_ctrl_passthru_mem_tl_intg_err.70042956430923134361987467897159070482184415864267761197337780062476134195759
Line 324, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_ERROR @ 1807594283 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1807594283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_partial_access_b2b has 2 failures.
6.sram_ctrl_partial_access_b2b.24128072785194031985366700077689324655266276888205434530091378609214836895138
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_partial_access_b2b/latest/run.log
UVM_ERROR @ 17614464404 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 17614464404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.sram_ctrl_partial_access_b2b.19442085174658074634086303931728849803613844530633903797131931804980246862811
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_partial_access_b2b/latest/run.log
UVM_ERROR @ 137307276 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 137307276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_executable has 1 failures.
8.sram_ctrl_executable.65971898714471285853103998950011838940121568161629318280695251960529835050750
Line 294, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 23379896501 ps: (sram_ctrl_scoreboard.sv:413) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 23379896501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more tests.
UVM_ERROR (sram_ctrl_scoreboard.sv:397) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 11 failures:
3.sram_ctrl_stress_all.28649807975703770778601607054700764571921729688694752095503428816811484752585
Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 3932253401 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 3932253401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.sram_ctrl_stress_all.57497562744331766611964633838072786278472449916964007771877349781495884701458
Line 325, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 10307391016 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 10307391016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
6.sram_ctrl_lc_escalation.78788090563294375883430698756357771251030352992695238043021178956311314155989
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 216646722 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 216646722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.sram_ctrl_lc_escalation.31301964593163502777963506209141537676056057838333747833237089084838257049254
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 451931852 ps: (sram_ctrl_scoreboard.sv:397) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 451931852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:827) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
4.sram_ctrl_stress_all_with_rand_reset.58090033486827827992625386177978061188160289312163861974393368984017824594022
Line 368, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2010700447 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2010700447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.sram_ctrl_stress_all_with_rand_reset.78301335259898035261147565743366602381419393675296355730224996087085054089334
Line 312, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 669655847 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 669655847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:
21.sram_ctrl_stress_all.85766387255450403817733676135596686077331958825660493857144188335594455085916
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 338176663 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 338176663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sram_ctrl_stress_all.16120990660565455931310265078231089309321587252449897029808736538037062029901
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 772138802 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 772138802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (sram_ctrl_base_vseq.sv:102) [sram_ctrl_bijection_vseq] Timed out waiting for key request done has 2 failures:
Test sram_ctrl_bijection has 1 failures.
28.sram_ctrl_bijection.6223293972156687751507477189803388198833934967949588944388267470278381019152
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/28.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 24177518195 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 24177518195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_stress_all has 1 failures.
37.sram_ctrl_stress_all.58838888845106471519228438757871768888308047808396715179433706385982277274476
Line 402, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 57332356077 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 57332356077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---