SRAM_CTRL/RET Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.197m	1.462ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	29.678us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	14.872us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.370s	710.254us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	98.850us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.430s	91.278us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	14.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	98.850us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	10.760s	6.239ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.040s	2.279ms	50	50	100.00
V1		TOTAL			185	205	90.24
V2	multiple_keys	sram_ctrl_multiple_keys	42.121m	28.407ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.913m	8.417ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.327m	19.760ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	31.028m	4.804ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	24.900s	1.602ms	43	50	86.00
V2	executable	sram_ctrl_executable	32.291m	7.716ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.277m	2.370ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.482m	108.639ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.659m	1.805ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.066m	151.353us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.970m	65.443ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.230s	57.570us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.888h	88.274ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.710s	17.055us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.750s	128.980us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.750s	128.980us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	29.678us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	14.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	98.850us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	30.913us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	29.678us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	14.872us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	98.850us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	30.913us	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	11.070s	1.604ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
		sram_ctrl_tl_intg_err	2.570s	385.382us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.570s	385.382us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.970m	65.443ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	14.872us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.291m	7.716ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.291m	7.716ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.291m	7.716ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	24.900s	1.602ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	11.070s	1.604ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.197m	1.462ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.197m	1.462ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.291m	7.716ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	24.900s	1.602ms	43	50	86.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.197m	1.462ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.250s	871.617us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.960m	9.872ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			955	1040	91.83

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	100.00	97.48	100.00	100.00	99.14	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 50 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 50 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.80042203224363530612873563691577365905363609803167503327580197449004988738795
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 184807380 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 184807380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.31617550220765320580256541021828983458955739759760685969529767352971941242767
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 531674022 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 531674022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 14 failures:

Test sram_ctrl_stress_all has 7 failures.

3.sram_ctrl_stress_all.28041476459037837893260943180268728103832239895166409896436046796253693523565
Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 9245902693 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 9245902693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.sram_ctrl_stress_all.46233881888543499192211472615039352946069739777878432482860532615216061524713
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1605193746 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 1605193746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sram_ctrl_lc_escalation has 7 failures.

11.sram_ctrl_lc_escalation.45727597868303576731286264730821275370024366843350138775508147411692385994186
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 1293154134 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 1293154134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sram_ctrl_lc_escalation.66329334957782816079279968073817849576874200538747039398146223117524394216827
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 171326551 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 171326551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 8 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 8 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.78885158959382894985284889313867799037910938185201551178580993653066704688641
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  32830932 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  32830932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.88463538746815149520528802791966479217405805706762924683879070787064359505622
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  91278354 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  91278354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 5 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 5 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.27413050254501850703044563832849567967461993527582316948491769337125117417346
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  27637753 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (12 [0xc] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  27637753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.112302158923341440543932387440537652465769389404646528214238231969844458000738
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100300582 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 100300582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.36503435646282225076354150077716289510253576202903114088490625141517718314217
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  90808957 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  90808957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.67352815694206126322565021953187878613085555216541926905435969263991664864439
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96258071 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  96258071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.31054617527789975507028673905812553093622780237292312581934247667603710381967
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96431625 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  96431625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.115312735075932349955253741354467710547366642359834732675812374223378545770336
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  33257743 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  33257743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.65950603638924260669972473508184430451030134282234895107441231769152838247625
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  30137591 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  30137591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.sram_ctrl_csr_mem_rw_with_rand_reset.98557544194219395970676236551866868336613149186949257948113234548112114156874
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  45586201 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  45586201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.49996802175217424666232840733980535501138319676055430344071167020238176907295
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26902178 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @  26902178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 35.sram_ctrl_regwen.83954763539046202360890212365965502829716901183709452136076393636724681150134
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 10213033994 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x6035ed83
  UVM_INFO @ 10213033994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```