0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.606m | 755.919us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.760s | 22.787us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.750s | 20.870us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.410s | 1.278ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.750s | 36.218us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 3.410s | 133.699us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.750s | 20.870us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.750s | 36.218us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 10.560s | 1.428ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 5.860s | 647.722us | 50 | 50 | 100.00 |
| V1 | TOTAL | 204 | 205 | 99.51 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 36.635m | 23.086ms | 47 | 50 | 94.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.766m | 4.268ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.379m | 10.843ms | 47 | 50 | 94.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 2.285m | 293.032us | 1 | 50 | 2.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 10.840s | 9.683ms | 42 | 50 | 84.00 |
| V2 | executable | sram_ctrl_executable | 28.897m | 60.973ms | 48 | 50 | 96.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.775m | 1.211ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 9.967m | 22.206ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.081m | 229.461us | 0 | 50 | 0.00 |
| sram_ctrl_throughput_w_partial_write | 2.534m | 523.329us | 0 | 50 | 0.00 | ||
| V2 | regwen | sram_ctrl_regwen | 32.120m | 18.703ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.840s | 38.506us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.531h | 58.212ms | 33 | 50 | 66.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.770s | 21.103us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 5.400s | 700.478us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 5.400s | 700.478us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.760s | 22.787us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.750s | 20.870us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 36.218us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 26.337us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.760s | 22.787us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.750s | 20.870us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 36.218us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.860s | 26.337us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 558 | 740 | 75.41 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.520s | 621.212us | 18 | 20 | 90.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.670s | 740.389us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.670s | 740.389us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 32.120m | 18.703ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.750s | 20.870us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 28.897m | 60.973ms | 48 | 50 | 96.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 28.897m | 60.973ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 28.897m | 60.973ms | 48 | 50 | 96.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.840s | 9.683ms | 42 | 50 | 84.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.520s | 621.212us | 18 | 20 | 90.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.606m | 755.919us | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.606m | 755.919us | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 28.897m | 60.973ms | 48 | 50 | 96.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.840s | 9.683ms | 42 | 50 | 84.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.606m | 755.919us | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.720s | 429.998us | 5 | 5 | 100.00 |
| V2S | TOTAL | 43 | 45 | 95.56 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 11.174m | 10.515ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 847 | 1040 | 81.44 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 8 | 50.00 |
| V2S | 3 | 3 | 2 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.44 | 100.00 | 98.18 | 100.00 | 100.00 | 99.71 | 99.70 | 98.52 |
UVM_ERROR (sram_ctrl_throughput_vseq.sv:44) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) has 100 failures:
0.sram_ctrl_max_throughput.54639359465327320633439165271712650528677000947673346599706001426787819661380
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
UVM_ERROR @ 62955343 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (3517 [0xdbd] vs 3325 [0xcfd])
UVM_INFO @ 62955343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_max_throughput.48133588094984454723472423325128204411912962355783719771685052014616982785487
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_max_throughput/latest/run.log
UVM_ERROR @ 178753868 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (2329 [0x919] vs 2321 [0x911])
UVM_INFO @ 178753868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.sram_ctrl_throughput_w_partial_write.41502908757542548494841825450097625691764121339150308948872719026662541743483
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest/run.log
UVM_ERROR @ 480308963 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (9370 [0x249a] vs 9362 [0x2492])
UVM_INFO @ 480308963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_throughput_w_partial_write.31019736785194333862001751920355481712388686913974755561138915650161566339939
Line 271, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_throughput_w_partial_write/latest/run.log
UVM_ERROR @ 83747123 ps: (sram_ctrl_throughput_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + 1 + num_partial_write * 2 (2022 [0x7e6] vs 2011 [0x7db])
UVM_INFO @ 83747123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 49 failures:
0.sram_ctrl_access_during_key_req.19039401738364175219789731310300509789719068602287609257092091685753637790242
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 967335569 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x59) != exp (0x6b)
UVM_INFO @ 967335569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.sram_ctrl_access_during_key_req.101390566541454495255201162560503267531275102557338687958257138990568300262540
Line 275, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_access_during_key_req/latest/run.log
UVM_ERROR @ 60250620 ps: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x54) != exp (0xa)
UVM_INFO @ 60250620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:415) [scoreboard] Check failed cfg.in_key_req == * (* [*] vs * [*]) No item is accepted during key req has 16 failures:
Test sram_ctrl_lc_escalation has 5 failures.
2.sram_ctrl_lc_escalation.36928749958382236459329324188070289742292761768899772888949236494472170162623
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 1706201343 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1706201343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.sram_ctrl_lc_escalation.62639745000572610588266654726107881335059235794378552503050045498944757158481
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 1836591093 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 1836591093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test sram_ctrl_executable has 2 failures.
2.sram_ctrl_executable.71116448188246685131001487827040957276841434247506710968807339240292393268892
Line 310, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 38540123668 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 38540123668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.sram_ctrl_executable.96564182360058985157283351489384091278416303665145631838051937439947722580422
Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest/run.log
UVM_ERROR @ 4893735777 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 4893735777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_passthru_mem_tl_intg_err has 2 failures.
6.sram_ctrl_passthru_mem_tl_intg_err.31183195440478138617496013202577743339033837661018330699596950218887034718011
Line 305, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_ERROR @ 489625776 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 489625776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.sram_ctrl_passthru_mem_tl_intg_err.99891923474977378676558438488397332249850276876160688058556176764657521577540
Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
UVM_ERROR @ 133440526 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 133440526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_multiple_keys has 3 failures.
8.sram_ctrl_multiple_keys.86095927569267544252663278557059598283622574388375951984785263847956549520194
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 2966315318 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 2966315318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.sram_ctrl_multiple_keys.62785765882380147541946903202712454359771910359130930353826243896349601779649
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_multiple_keys/latest/run.log
UVM_ERROR @ 6175427645 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 6175427645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
15.sram_ctrl_stress_all_with_rand_reset.109230705025170764286541306540693638167728237368094110695683882224970662387998
Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 548948870 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 548948870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.sram_ctrl_stress_all_with_rand_reset.665681008349302005992647400997676951771624131280037898216330429658609690427
Line 500, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3797225176 ps: (sram_ctrl_scoreboard.sv:415) [uvm_test_top.env.scoreboard] Check failed cfg.in_key_req == 0 (1 [0x1] vs 0 [0x0]) No item is accepted during key req
UVM_INFO @ 3797225176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more tests.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 8 failures:
5.sram_ctrl_stress_all.78460590146673436058389721690405435081678665829237606766109362585046105570572
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 707718673 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 707718673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.sram_ctrl_stress_all.67421322509023416750577590393673475275987238214580489066814742339446996162590
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 232086098 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 232086098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (sram_ctrl_scoreboard.sv:399) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 6 failures:
7.sram_ctrl_stress_all.107352794701412536816211863292376929916800787292553465021518972298432732447614
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 2979233980 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 2979233980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.sram_ctrl_stress_all.2714559141928512737441223966546728860809629881027422260517291801236299820711
Line 359, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 15053327626 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 15053327626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
11.sram_ctrl_lc_escalation.102169540306830509248407033347040935693013579381695798159751436458781616290713
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 1735899117 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 1735899117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_lc_escalation.109416713272455307693527137965495304865906702465760327331814995503689133528158
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_lc_escalation/latest/run.log
UVM_ERROR @ 1365038615 ps: (sram_ctrl_scoreboard.sv:399) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
UVM_INFO @ 1365038615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (sram_ctrl_base_vseq.sv:102) [sram_ctrl_bijection_vseq] Timed out waiting for key request done has 6 failures:
14.sram_ctrl_stress_all.51400301634662249144956162772137357045081046111831968415358801003341006371792
Line 433, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 38413913599 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 38413913599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.sram_ctrl_stress_all.70004572201828820200260910538805982996982286508929720110671085244544870454249
Line 433, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
UVM_FATAL @ 31848396571 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 31848396571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
37.sram_ctrl_bijection.84035303410092937706198854694884414085266295519397582909522081643258314055605
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 26457718697 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 26457718697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.sram_ctrl_bijection.41128871612275665594626001405048170734729015755961683784966785231463667321792
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_bijection/latest/run.log
UVM_FATAL @ 11735309699 ps: (sram_ctrl_base_vseq.sv:102) [uvm_test_top.env.virtual_sequencer.sram_ctrl_bijection_vseq] Timed out waiting for key request done
UVM_INFO @ 11735309699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:815) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
29.sram_ctrl_stress_all_with_rand_reset.78518668734510558067051484366366223224192934705456659139373408017048023048178
Line 361, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4295381932 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4295381932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.sram_ctrl_stress_all_with_rand_reset.5270673190374092918192361860605430337494155481414333034267604129487703991798
Line 397, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3795778271 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3795778271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (mem_bkdr_scb.sv:130) [mem_bkdr_scb] Check failed act_data == exp_item.data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
15.sram_ctrl_stress_all.9765566784398264466175308911382614706679567749894511438801925652486197359804
Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log
UVM_ERROR @ 3946681836 ps: (mem_bkdr_scb.sv:130) [mem_bkdr_scb] Check failed act_data == exp_item.data (67586939 [0x4074b7b] vs 1030307335 [0x3d693e07]) addr 0xffc read out mismatch
UVM_INFO @ 3946681836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
16.sram_ctrl_csr_mem_rw_with_rand_reset.95169714847333113570994502727138745286790559874264806358024563082035774887369
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 133699239 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 8 [0x8]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 133699239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---