SRAM_CTRL/RET Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.760m	1.058ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	68.588us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	156.579us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.490s	679.888us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	17.171us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.870s	38.784us	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	156.579us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	17.171us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.440s	3.267ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.790s	166.364us	50	50	100.00
V1		TOTAL			185	205	90.24
V2	multiple_keys	sram_ctrl_multiple_keys	27.441m	7.377ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.778m	42.966ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.560m	34.560ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	36.826m	67.034ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	44.100s	1.345ms	44	50	88.00
V2	executable	sram_ctrl_executable	32.453m	23.912ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.505m	807.360us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.521m	27.935ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.699m	266.499us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.873m	675.937us	50	50	100.00
V2	regwen	sram_ctrl_regwen	53.169m	96.002ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.190s	90.857us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.944h	80.155ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.730s	14.323us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.770s	146.277us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.770s	146.277us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	68.588us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	156.579us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	17.171us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	90.924us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	68.588us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	156.579us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	17.171us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	90.924us	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	11.460s	847.388us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
		sram_ctrl_tl_intg_err	2.600s	209.454us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.600s	209.454us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	53.169m	96.002ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	156.579us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.453m	23.912ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.453m	23.912ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.453m	23.912ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	44.100s	1.345ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	11.460s	847.388us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.760m	1.058ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.760m	1.058ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.453m	23.912ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	44.100s	1.345ms	44	50	88.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.760m	1.058ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.060s	227.911us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.616m	655.518us	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			958	1040	92.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.26	100.00	97.48	100.00	100.00	99.14	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:774) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses. has 50 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 50 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.527983417507757337339242151881123782314947261076294044548327985605807436576
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1683649113 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 1683649113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.10221715834740601296833237670983095218792481469978814552258915859474628182865
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 853690075 ps: (cip_base_vseq.sv:774) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_INFO @ 853690075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 48 more failures.

UVM_ERROR (sram_ctrl_scoreboard.sv:371) [scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= * (* [*] vs * [*]) has 12 failures:

Test sram_ctrl_stress_all has 6 failures.

0.sram_ctrl_stress_all.47248310008331071880111101898624075767381330210249048289516270422010957084707
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 1568323797 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 1568323797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.sram_ctrl_stress_all.64180889616075929796403530735247634945109388460923014873974306730478910859835
Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 500086817 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 500086817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test sram_ctrl_lc_escalation has 6 failures.

8.sram_ctrl_lc_escalation.13608174061920702530488376814170805259698452513640876899774969353486099376771
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 265560649 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 265560649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sram_ctrl_lc_escalation.31631643475764698229036608200826612637493647462951167364504918783371933836051
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_lc_escalation/latest/run.log

  UVM_ERROR @ 187249785 ps: (sram_ctrl_scoreboard.sv:371) [uvm_test_top.env.scoreboard] Check failed mem_bkdr_scb.read_item_q.size + mem_bkdr_scb.write_item_q.size <= 6 (7 [0x7] vs 6 [0x6])
  UVM_INFO @ 187249785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 9 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 9 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.57874232138536649096322539579394948764471978133262679712791469030460659800030
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26921527 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  26921527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.51086948754277151167086840817552693036674849025990847327286357920099822351666
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  60869124 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  60869124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 4 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 4 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.78501698660981738753040325922298454171343207743620773973254757156656796204070
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 122672330 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 122672330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.sram_ctrl_csr_mem_rw_with_rand_reset.106788136479313710105956127433729400347396230156514211019165329008291114689595
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22082451 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (14 [0xe] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  22082451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 3 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 3 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.79234591666958996778698494665758481862915188037199837187077701710218930942333
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  72210258 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  72210258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.49645629113429270505431363521374178597941783024862883761082127340078413676030
    Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  92159512 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  92159512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.57212196853311583679748332002479766167228985941038690301718233654635955444581
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  26035589 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  26035589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.96103983576629384923290152346158392654993545760256460595266650232438203979592
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28884490 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  28884490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.78906913122706482186056916174421285034297773164714775151308344851771709681960
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  93525444 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  93525444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.48673277950939302584605968624174784019379789967815707464149750726426795471340
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28115169 ps: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_seed_valid reset value: 0x0
  UVM_INFO @  28115169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```