SRAM_CTRL/RET Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.539m	3.195ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	21.199us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	36.553us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.950s	151.524us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.820s	77.676us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.460s	79.091us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	36.553us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	77.676us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.710s	9.319ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.730s	838.959us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	48.309m	18.333ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.635m	16.748ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.488m	20.790ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	33.949m	4.919ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.250s	1.677ms	50	50	100.00
V2	executable	sram_ctrl_executable	36.207m	8.224ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.721m	1.383ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.339m	24.235ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.571m	272.992us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.354m	611.020us	50	50	100.00
V2	regwen	sram_ctrl_regwen	27.362m	18.208ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.820s	27.688us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.741h	706.417ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.700s	86.647us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.000s	1.412ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.000s	1.412ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	21.199us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	36.553us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	77.676us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	47.318us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	21.199us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	36.553us	20	20	100.00
		sram_ctrl_csr_aliasing	0.820s	77.676us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	47.318us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.710s	6.430ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
		sram_ctrl_tl_intg_err	2.830s	519.224us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.830s	519.224us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	27.362m	18.208ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	36.553us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	36.207m	8.224ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	36.207m	8.224ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	36.207m	8.224ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.250s	1.677ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.710s	6.430ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.539m	3.195ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.539m	3.195ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	36.207m	8.224ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.250s	1.677ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.539m	3.195ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.390s	383.183us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.269m	1.886ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1019	1040	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 11.sram_ctrl_stress_all_with_rand_reset.1047094401641540389698929757831075580371193443477798932054793497544322415879
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1336879020 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1336879020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_stress_all_with_rand_reset.59712394539544148262780688415200272653552863063810456270688960651764116412511
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2802034858 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2802034858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:

Test sram_ctrl_stress_all has 6 failures.

0.sram_ctrl_stress_all.27500989470306121429533316395902282505130948981416914448602839171623921600114
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  62980171 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  62980171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.sram_ctrl_stress_all.107305128435049854409292798107030807542325969115207327654170315331860387022508
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 268526408 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 268526408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.75642796972542088552091496704474276380971356046295805838733688010815142307880
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96990695 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  96990695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.38287557671693185840812396612854574702872111307526703024121557480633248362394
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48771191 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  48771191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 2 failures.
  - 17.sram_ctrl_executable.114501260107388802302935884694838232000563736299041088929318048585600479157388
    Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 95783128079 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xba5279a2
  UVM_INFO @ 95783128079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_executable.67896500213927776465715768323650563005253755901753825704910214916572967406837
    Line 324, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 155764135157 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9f26f0c6
  UVM_INFO @ 155764135157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 1.sram_ctrl_regwen.106623339241111822254189579839582918085360496848172459864170136273349824115605
    Line 301, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 78762075174 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xca440a57
  UVM_INFO @ 78762075174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.90071982956743954828745508531958014219742787236783641882014338644701445059489
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  43191394 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  43191394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```