SRAM_CTRL/RET Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.587m	143.962us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	46.466us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	12.052us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.470s	1.624ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	59.007us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.230s	75.319us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	12.052us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.007us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.320s	2.851ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.730s	551.914us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	29.478m	15.966ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.293m	15.773ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.486m	31.767ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	32.369m	56.507ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.190s	3.841ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.820m	12.925ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.659m	1.936ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.240m	265.642ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.634m	583.382us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.797m	158.724us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.628m	12.322ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.810s	167.720us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.218h	59.167ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.740s	16.117us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.910s	607.433us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.910s	607.433us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	46.466us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	12.052us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.007us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	100.219us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	46.466us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	12.052us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.007us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	100.219us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.000s	6.369ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.330s	1.856ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.330s	1.856ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.628m	12.322ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	12.052us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.820m	12.925ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.820m	12.925ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.820m	12.925ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.190s	3.841ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.000s	6.369ms	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.587m	143.962us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.587m	143.962us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.820m	12.925ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.190s	3.841ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.587m	143.962us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.070s	2.179ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.537m	2.635ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1020	1040	98.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.53897729335865104813604327578605825850854556470216058518843184822148444022873
    Line 303, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1126797464 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1126797464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_stress_all_with_rand_reset.67966626832912992702695911435114066443504814442640838009396861630921145989477
    Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2636178532 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2636178532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

11.sram_ctrl_stress_all.18795442561209555578439224839804094280315389536391373944819003161932664208513
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 106128896 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 106128896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.sram_ctrl_stress_all.78969830221964353898198360786772705226578200575305932132647622033709503569480
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  20269847 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  20269847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.110799386472883621970340488426156980268594818341678574347816844265862205777458
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  90330143 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  90330143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_csr_mem_rw_with_rand_reset.110764381040128534975541075384203092569491441981390957233257049396590542007913
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  43509187 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  43509187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 36.sram_ctrl_regwen.38347956825543902658757480195992745403445519100677454422023488024270332768922
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 47114012582 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x88be53da
  UVM_INFO @ 47114012582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.sram_ctrl_regwen.107473342405925702878047409116318947203370545473947393621520614949407396949637
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/45.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 35495746433 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x5e6c2242
  UVM_INFO @ 35495746433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.24856598092668965609725057987997966189116416688606452604320144787891549438056
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  75318833 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  75318833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 36.sram_ctrl_executable.63730994699958108479404212525706088701709619692495212702846647670250142492116
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 20306763120 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x6510dc26
  UVM_INFO @ 20306763120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```