SRAM_CTRL/RET Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.982m	635.304us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	20.720us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	142.110us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.110s	235.820us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	71.275us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	12.120s	10.005ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	142.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	71.275us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.260s	4.314ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.700s	316.839us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	25.122m	3.347ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.225m	15.567ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.526m	30.016ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.374m	9.201ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.780s	3.878ms	50	50	100.00
V2	executable	sram_ctrl_executable	37.464m	22.890ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.995m	2.799ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.744m	117.600ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.612m	1.609ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.727m	295.969us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.443m	258.435ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.170s	153.766us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.449h	18.402ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.690s	42.912us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.150s	146.279us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.150s	146.279us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	20.720us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	142.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	71.275us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	226.278us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	20.720us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	142.110us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	71.275us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.800s	226.278us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.400s	440.296us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
		sram_ctrl_tl_intg_err	3.000s	603.705us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.000s	603.705us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.443m	258.435ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	142.110us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	37.464m	22.890ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	37.464m	22.890ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	37.464m	22.890ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.780s	3.878ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.400s	440.296us	20	20	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.982m	635.304us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.982m	635.304us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	37.464m	22.890ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.780s	3.878ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.982m	635.304us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.370s	789.905us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.249m	2.058ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1023	1040	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.09	99.81	97.02	100.00	100.00	98.58	99.70	98.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 10 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.58938355605345850933867463084480762405465073449900260335944983274773877553747
    Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 813257035 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 813257035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.sram_ctrl_stress_all_with_rand_reset.7961125267807081048459983673367167613684252841668241843617026089382009712428
    Line 383, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12003996592 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12003996592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

2.sram_ctrl_stress_all.85999693957887956443516535369794805279171975838438496294606621287976851105633
Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  80180279 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  80180279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sram_ctrl_stress_all.20885802979056601236494193300028854010271726260436562754489564350286811729694
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  26509008 ps: (tlul_assert.sv:272) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  26509008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 7.sram_ctrl_stress_all.476907150660596470862297836796137880087258717910429492666171652493558694997
    Line 333, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 172968790955 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xba030478
  UVM_INFO @ 172968790955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_executable has 1 failures.
  - 43.sram_ctrl_executable.52644133777661287508837685071925168822984669792446332746921737809654360795100
    Line 282, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 25935590871 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x618e09f7
  UVM_INFO @ 25935590871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.27736755884083575169826327650649060807849985638255207796804889969140114499233
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116860165 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @ 116860165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:92) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.101521371042573460966864115345069505705978589225491214391691312457553942791109
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004679295 ps: (sram_ctrl_base_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10004679295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 49.sram_ctrl_multiple_keys.17410275148820675695160866702526194107949817218172636744453236015128191432063
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/49.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 27914113819 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc2f82262
  UVM_INFO @ 27914113819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```