SRAM_CTRL/RET Simulation Results

Saturday June 22 2024 23:02:20 UTC

GitHub Revision: 8fdb25c8d9

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 116774179587740886356693500529232784059703555433764635649168222249757162669

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.669m 145.307us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 63.622us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 109.927us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.340s 333.001us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.780s 46.314us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.350s 41.055us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 109.927us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 46.314us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.790s 2.598ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.710s 1.676ms 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 33.182m 58.789ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.796m 4.288ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.505m 5.760ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 41.264m 7.213ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.670s 1.678ms 50 50 100.00
V2 executable sram_ctrl_executable 30.375m 28.961ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.230m 719.714us 50 50 100.00
sram_ctrl_partial_access_b2b 9.990m 122.047ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.609m 719.717us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.649m 162.766us 50 50 100.00
V2 regwen sram_ctrl_regwen 47.407m 25.334ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.850s 64.066us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.796h 419.076ms 44 50 88.00
V2 alert_test sram_ctrl_alert_test 0.740s 30.779us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.860s 486.805us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.860s 486.805us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 63.622us 5 5 100.00
sram_ctrl_csr_rw 0.730s 109.927us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 46.314us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 32.969us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 63.622us 5 5 100.00
sram_ctrl_csr_rw 0.730s 109.927us 20 20 100.00
sram_ctrl_csr_aliasing 0.780s 46.314us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 32.969us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.530s 1.550ms 19 20 95.00
V2S tl_intg_err sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
sram_ctrl_tl_intg_err 2.510s 855.776us 19 20 95.00
V2S prim_count_check sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.510s 855.776us 19 20 95.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 47.407m 25.334ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 109.927us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 30.375m 28.961ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 30.375m 28.961ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 30.375m 28.961ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.670s 1.678ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.530s 1.550ms 19 20 95.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.669m 145.307us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.669m 145.307us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.669m 145.307us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 30.375m 28.961ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.670s 1.678ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.669m 145.307us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.630s 492.983us 5 5 100.00
V2S TOTAL 43 45 95.56
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 10.395m 1.434ms 46 50 92.00
V3 TOTAL 46 50 92.00
TOTAL 1027 1040 98.75

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 1 33.33
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results