25e609d6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.706m | 2.356ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.740s | 28.310us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.720s | 12.615us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 1.970s | 175.127us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.710s | 14.972us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 5.940s | 10.010ms | 14 | 20 | 70.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.720s | 12.615us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.710s | 14.972us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 12.120s | 685.489us | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 6.390s | 1.279ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 199 | 205 | 97.07 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 30.368m | 176.286ms | 49 | 50 | 98.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 6.846m | 17.383ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.451m | 4.701ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 46.797m | 4.452ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 11.050s | 3.574ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 35.080m | 73.295ms | 49 | 50 | 98.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.664m | 1.299ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 10.787m | 47.785ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.807m | 748.703us | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.468m | 546.206us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 30.248m | 4.024ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.880s | 389.574us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 2.266h | 79.797ms | 44 | 50 | 88.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.700s | 16.132us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 5.050s | 148.082us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 5.050s | 148.082us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.740s | 28.310us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 12.615us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.710s | 14.972us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.880s | 43.763us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.740s | 28.310us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 0.720s | 12.615us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.710s | 14.972us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.880s | 43.763us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 732 | 740 | 98.92 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 3.390s | 548.897us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 3.440s | 4.938ms | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 3.440s | 4.938ms | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 30.248m | 4.024ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.720s | 12.615us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 35.080m | 73.295ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 35.080m | 73.295ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 35.080m | 73.295ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 11.050s | 3.574ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 3.390s | 548.897us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.706m | 2.356ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.706m | 2.356ms | 50 | 50 | 100.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.706m | 2.356ms | 50 | 50 | 100.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 35.080m | 73.295ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 11.050s | 3.574ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.706m | 2.356ms | 50 | 50 | 100.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 2.370s | 233.782us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 19.049m | 2.913ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 1018 | 1040 | 97.88 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 16 | 16 | 13 | 81.25 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
4.sram_ctrl_stress_all_with_rand_reset.27069151953742592343292041274067800569086681105910591975488094994321937423958
Line 377, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11422444136 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 11422444136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.sram_ctrl_stress_all_with_rand_reset.54547858695460885287132947540290258018250309077839033737763404732908584644551
Line 330, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6856368071 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 6856368071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:
13.sram_ctrl_stress_all.99040718594162484407945519158482011601383787933623318068190817452983074593258
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 107653313 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 107653313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.sram_ctrl_stress_all.80271199743510549098001499704162718123788253742622145712679496731173320252505
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 69371598 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 69371598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
5.sram_ctrl_csr_mem_rw_with_rand_reset.58121508181014340857527092196428245321603713610199639525380716296480287485614
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 126278555 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 126278555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.sram_ctrl_csr_mem_rw_with_rand_reset.92422002009956545119690084473973703126516436429475153996332258892089989171587
Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 34770213 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
UVM_INFO @ 34770213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(rdata_o))' has 2 failures:
11.sram_ctrl_stress_all.53838233295591875615115425646409186678076859558306922820773870045489074253357
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 57854363 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 57854363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.sram_ctrl_stress_all.12072541272954502583966992341839024174828764683947507806805621954172746520402
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 501758869 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 501758869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
3.sram_ctrl_csr_mem_rw_with_rand_reset.80181121983784758908108129366229896634818709371401684332101845690656819961422
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 22727815 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
UVM_INFO @ 22727815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
7.sram_ctrl_csr_mem_rw_with_rand_reset.100116777620367966336955285468775276578246395968636162263557817956153906991559
Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_FATAL @ 10009596222 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
UVM_INFO @ 10009596222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
11.sram_ctrl_stress_all_with_rand_reset.52426675214152129104593818119562322670386461453617560829113235070190874146859
Line 341, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2717861587 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2717861587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
15.sram_ctrl_csr_mem_rw_with_rand_reset.106602832563728716046721608273893379039153463373192847698907108942782950559963
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 101067090 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 101067090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
18.sram_ctrl_csr_mem_rw_with_rand_reset.5549184727425012362662927024582958549665509022013462168957557649866277739743
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 51140360 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
UVM_INFO @ 51140360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
29.sram_ctrl_executable.95108083263731176382948587030075519356588195603115936936451307051097442648930
Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_executable/latest/run.log
UVM_FATAL @ 11055722869 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x9030120f
UVM_INFO @ 11055722869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
40.sram_ctrl_multiple_keys.7456034301394453346145460991027587781196511219188421536961908846577469896214
Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/40.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 75868781872 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xcdcc841c
UVM_INFO @ 75868781872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---