SRAM_CTRL/RET Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: `6e698b4dfe`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.651m	145.637us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	47.193us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	20.363us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.380s	1.047ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	21.830us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.510s	72.060us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	20.363us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.830us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.710s	2.624ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.010s	703.135us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	29.520m	215.762ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.860m	4.314ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.530m	18.748ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.393m	6.820ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.640s	14.822ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.291m	14.542ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.583m	817.796us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.983m	25.618ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.595m	142.517us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.613m	605.807us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.607m	13.687ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	30.688us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.200h	102.752ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.730s	15.840us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.290s	232.665us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.290s	232.665us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	47.193us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	20.363us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.830us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	76.191us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	47.193us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	20.363us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.830us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	76.191us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.060s	657.101us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
		sram_ctrl_tl_intg_err	2.850s	1.305ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.850s	1.305ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.607m	13.687ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	20.363us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.291m	14.542ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.291m	14.542ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.291m	14.542ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.640s	14.822ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.060s	657.101us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.651m	145.637us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.651m	145.637us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.651m	145.637us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.291m	14.542ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.640s	14.822ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.651m	145.637us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.090s	278.685us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.214m	2.650ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.5474996859995724013832029540075408484347851745115118946900686085392445528171
    Line 368, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4859830337 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4859830337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_stress_all_with_rand_reset.6779720994583213985628942011904943809950042051283016530566754573435772512317
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1217691682 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1217691682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

6.sram_ctrl_stress_all.21634347106066601543017607790210411543141284285071948068487391883718388571759
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  97622388 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  97622388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.sram_ctrl_stress_all.105399698507643456608135890047825409694204060750554640095373571960004103958450
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 313299032 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 313299032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.85482101642555993144908062043047490870961416490305805724415021798157180127196
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  33077588 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  33077588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.71131122245089099751321032560575817755725193812627568808402912839530064995546
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23509050 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  23509050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 10.sram_ctrl_stress_all.1115210058853692279970462443708271976779316956715183204002327325893321222853
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 171700357 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 171700357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 24.sram_ctrl_stress_all.79929112910527601462880495770084911781443373749591026960449710763366797022721
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 708350947 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 708350947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 10.sram_ctrl_csr_mem_rw_with_rand_reset.75412648477202226004764161041769837051130359624624760700794849666154975048666
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 377765565 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 377765565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```