SRAM_CTRL/RET Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.684m	745.793us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	15.453us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	15.385us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	570.269us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.810s	32.920us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.990s	36.794us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	15.385us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	32.920us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.200s	3.629ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.080s	385.578us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	37.314m	34.482ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.411m	9.496ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.447m	14.512ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	34.444m	11.186ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.220s	3.857ms	50	50	100.00
V2	executable	sram_ctrl_executable	49.355m	3.966ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.468m	1.335ms	49	50	98.00
		sram_ctrl_partial_access_b2b	12.935m	189.804ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.487m	531.864us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.382m	756.323us	50	50	100.00
V2	regwen	sram_ctrl_regwen	33.994m	17.966ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.840s	28.128us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.098h	40.156ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.750s	15.652us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.060s	140.762us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.060s	140.762us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	15.453us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.385us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	32.920us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	68.547us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	15.453us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.385us	20	20	100.00
		sram_ctrl_csr_aliasing	0.810s	32.920us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	68.547us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.510s	568.906us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	266.527us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	266.527us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	33.994m	17.966ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	15.385us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	49.355m	3.966ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	49.355m	3.966ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	49.355m	3.966ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.220s	3.857ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.510s	568.906us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.684m	745.793us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.684m	745.793us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.684m	745.793us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	49.355m	3.966ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.220s	3.857ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.684m	745.793us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.690s	699.819us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.238m	6.303ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1026	1040	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:828) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 8 failures.
  - 3.sram_ctrl_stress_all_with_rand_reset.90356214586574557640094819921492680710383271825402937452529495304959037502188
    Line 301, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 949644761 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 949644761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.sram_ctrl_stress_all_with_rand_reset.9745638795553824970412047780121205314099740782673367174113341487724643490426
    Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10025530472 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10025530472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

34.sram_ctrl_stress_all.79953616236447419746430474230227003838590413011008503359213858960305406025023
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1737750450 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1737750450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.sram_ctrl_stress_all.39213158174419769896831608833752742773494193332722433960223107151212773562929
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  99380680 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  99380680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 8.sram_ctrl_regwen.39654905273361212119530423682632130393819160862267604109624628587989385398989
    Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 159360392862 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xc72ef672
  UVM_INFO @ 159360392862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 21.sram_ctrl_stress_all_with_rand_reset.108163812892421406268861058159724165595530284467385487318094651391533252579757
    Line 516, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/21.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26678507595 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 26678507595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 31.sram_ctrl_stress_all.55085116433224117833226284481001652912172082341422172553282332648024275879168
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  39888526 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  39888526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:250) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 48.sram_ctrl_partial_access.16968910288545022161349839623386800320835183182735101665989073917706975798044
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10317999838 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x3d58aaa1
  UVM_INFO @ 10317999838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```