SRAM_CTRL/RET Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.494m 3.638ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.740s 14.527us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 27.274us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.330s 453.730us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 67.705us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.090s 126.745us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 27.274us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 67.705us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.350s 2.730ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.040s 233.086us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 28.844m 154.190ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.050m 8.799ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.427m 51.855ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.221m 3.291ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.270s 3.477ms 50 50 100.00
V2 executable sram_ctrl_executable 31.675m 17.353ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.586m 649.660us 50 50 100.00
sram_ctrl_partial_access_b2b 10.069m 26.431ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.559m 133.367us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.664m 639.186us 50 50 100.00
V2 regwen sram_ctrl_regwen 29.908m 16.672ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.880s 57.162us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.769h 97.280ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.750s 14.850us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.860s 520.729us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.860s 520.729us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.740s 14.527us 5 5 100.00
sram_ctrl_csr_rw 0.710s 27.274us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 67.705us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 183.401us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.740s 14.527us 5 5 100.00
sram_ctrl_csr_rw 0.710s 27.274us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 67.705us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 183.401us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.960s 982.918us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
sram_ctrl_tl_intg_err 3.240s 1.834ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.240s 1.834ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 29.908m 16.672ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 27.274us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 31.675m 17.353ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 31.675m 17.353ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 31.675m 17.353ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.270s 3.477ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.960s 982.918us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.494m 3.638ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.494m 3.638ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.494m 3.638ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 31.675m 17.353ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.270s 3.477ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.494m 3.638ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.340s 3.588ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.527m 7.947ms 43 50 86.00
V3 TOTAL 43 50 86.00
TOTAL 1026 1040 98.65

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results