SRAM_CTRL/RET Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.722m 552.713us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.730s 25.594us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.750s 15.023us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.470s 346.599us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 69.949us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.360s 54.337us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.750s 15.023us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 69.949us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 15.740s 13.168ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.550s 382.778us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 35.623m 76.117ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.691m 3.954ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.498m 68.253ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 33.410m 9.533ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 12.160s 7.112ms 50 50 100.00
V2 executable sram_ctrl_executable 33.185m 59.752ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.914m 634.327us 50 50 100.00
sram_ctrl_partial_access_b2b 10.697m 113.925ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.962m 138.314us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.703m 160.039us 50 50 100.00
V2 regwen sram_ctrl_regwen 27.623m 57.792ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.860s 246.379us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.779h 249.079ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.760s 202.128us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.070s 137.458us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.070s 137.458us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.730s 25.594us 5 5 100.00
sram_ctrl_csr_rw 0.750s 15.023us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 69.949us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 24.939us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.730s 25.594us 5 5 100.00
sram_ctrl_csr_rw 0.750s 15.023us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 69.949us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.860s 24.939us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.450s 3.766ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
sram_ctrl_tl_intg_err 2.580s 652.198us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.580s 652.198us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 27.623m 57.792ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.750s 15.023us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 33.185m 59.752ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 33.185m 59.752ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 33.185m 59.752ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 12.160s 7.112ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.450s 3.766ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.722m 552.713us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.722m 552.713us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.722m 552.713us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 33.185m 59.752ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 12.160s 7.112ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.722m 552.713us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 2.710s 2.641ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 15.763m 1.645ms 39 50 78.00
V3 TOTAL 39 50 78.00
TOTAL 1023 1040 98.37

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26

Failure Buckets

Past Results