SRAM_CTRL/RET Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.079m	445.439us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	44.380us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	14.290us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.230s	391.027us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	30.212us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.240s	235.862us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	14.290us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	30.212us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.420s	2.741ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.290s	193.381us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	25.014m	4.718ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.624m	4.077ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.531m	6.246ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.890m	103.606ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.480s	9.181ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.657m	21.308ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.640m	6.819ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.938m	200.207ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.409m	133.340us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.618m	155.763us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.432m	39.593ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.850s	82.529us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.576h	15.431ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.820s	17.373us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.260s	140.266us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.260s	140.266us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	44.380us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	14.290us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	30.212us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	26.010us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	44.380us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	14.290us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	30.212us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	26.010us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.920s	1.177ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
		sram_ctrl_tl_intg_err	2.410s	662.918us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.410s	662.918us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.432m	39.593ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	14.290us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.657m	21.308ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.657m	21.308ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.657m	21.308ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.480s	9.181ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.920s	1.177ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	3.079m	445.439us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.079m	445.439us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.079m	445.439us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.657m	21.308ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.480s	9.181ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.079m	445.439us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.130s	292.497us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.834m	8.262ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 2.sram_ctrl_stress_all_with_rand_reset.11697048276777402229595628981405923137734062593952142088785242984695951639991
    Line 293, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2693315672 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2693315672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.sram_ctrl_stress_all_with_rand_reset.76256818458289174977325352629962807418452293067481159853370729630695109398347
    Line 299, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/29.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 666976420 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 666976420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:

Test sram_ctrl_stress_all has 6 failures.

14.sram_ctrl_stress_all.96533860317552329024566794668447477888201506654483443180076113929228962105492
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  83166599 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  83166599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.sram_ctrl_stress_all.3308187563521195124788650002771564574516011206535534663905468201926065751850
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  22106885 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  22106885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.109996770243014788590504580715582337358735269352619204876215410204201259670369
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130341419 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 130341419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.57924196751613103652373820057916510500889234091882867773712594173932396600259
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 235862261 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (6 [0x6] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 235862261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 35.sram_ctrl_stress_all.107192622693935203498944298646443827903853469652262448646477305771541987533622
    Line 427, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 7706770786 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0xd7 [11010111] vs 0x7e [1111110]) addr 0xa9ebd360 read out mismatch
  UVM_INFO @ 7706770786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```