SRAM_CTRL/RET Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.441m	2.943ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	61.110us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.740s	26.368us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.060s	339.956us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.840s	66.241us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	67.962us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.740s	26.368us	20	20	100.00
		sram_ctrl_csr_aliasing	0.840s	66.241us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.550s	2.755ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.180s	336.613us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	33.414m	19.390ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.472m	4.470ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.496m	35.921ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	40.350m	4.855ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.990s	10.781ms	50	50	100.00
V2	executable	sram_ctrl_executable	29.768m	47.633ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.265m	3.129ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.939m	96.230ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.977m	493.833us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.766m	153.085us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.509m	13.605ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	306.496us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.129h	174.227ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.700s	50.554us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.270s	300.971us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.270s	300.971us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	61.110us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	26.368us	20	20	100.00
		sram_ctrl_csr_aliasing	0.840s	66.241us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	90.606us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	61.110us	5	5	100.00
		sram_ctrl_csr_rw	0.740s	26.368us	20	20	100.00
		sram_ctrl_csr_aliasing	0.840s	66.241us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.890s	90.606us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.080s	4.428ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
		sram_ctrl_tl_intg_err	3.100s	2.265ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.100s	2.265ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.509m	13.605ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.740s	26.368us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	29.768m	47.633ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	29.768m	47.633ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	29.768m	47.633ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.990s	10.781ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.080s	4.428ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.441m	2.943ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.441m	2.943ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.441m	2.943ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	29.768m	47.633ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.990s	10.781ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.441m	2.943ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.410s	1.169ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.851m	2.026ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.22818468166867566153844297328495368804332261445377395279387315798979744014037
    Line 346, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3797069011 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3797069011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.sram_ctrl_stress_all_with_rand_reset.54341626976988665080110524014210064446494921227158226074824634376371454346699
    Line 308, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4419365947 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4419365947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

14.sram_ctrl_stress_all.59114355187009562452520920506837055065085405412343507366833260544900020709488
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 351265003 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 351265003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.sram_ctrl_stress_all.97985210640455751082435547806508165119547653836706787111407505951991797157489
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  66433367 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  66433367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 7.sram_ctrl_regwen.21698204559236298065539762682596619681224525481637334415040353733079846745905
    Line 281, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 25675202039 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x9ea330f8
  UVM_INFO @ 25675202039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.sram_ctrl_regwen.12859776105967450451564511880591852650370176231634537649064374900371169804840
    Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 62461148144 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x834536a6
  UVM_INFO @ 62461148144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 32.sram_ctrl_stress_all.92720084518515037361082072649388417718578742676816392063919457662523187852767
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10500719824 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa1330d2f
  UVM_INFO @ 10500719824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.99099872468470117772962192018279234834687690327068153400255435643162168991742
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48173103 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  48173103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.35398521633652482645157310967358634406978533614943696930349990348317098104877
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  57460746 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  57460746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```