SRAM_CTRL/RET Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.786m	300.558us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.730s	14.700us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	15.199us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.200s	474.720us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	51.659us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.190s	340.470us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	15.199us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	51.659us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.860s	7.303ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.030s	651.918us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	32.508m	4.425ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.628m	8.243ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.463m	10.584ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.457m	3.165ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.160s	3.142ms	50	50	100.00
V2	executable	sram_ctrl_executable	41.799m	163.362ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.730m	1.427ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.277m	100.600ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.677m	138.771us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.766m	161.558us	50	50	100.00
V2	regwen	sram_ctrl_regwen	34.084m	4.378ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.820s	81.642us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.897h	15.537ms	45	50	90.00
V2	alert_test	sram_ctrl_alert_test	0.730s	18.963us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.900s	145.802us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.900s	145.802us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.730s	14.700us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.199us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	51.659us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	29.346us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.730s	14.700us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	15.199us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	51.659us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	29.346us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.060s	768.989us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	949.123us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	949.123us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	34.084m	4.378ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	15.199us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	41.799m	163.362ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	41.799m	163.362ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	41.799m	163.362ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.160s	3.142ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.060s	768.989us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.786m	300.558us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.786m	300.558us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.786m	300.558us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	41.799m	163.362ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.160s	3.142ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.786m	300.558us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.960s	994.745us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.599m	9.684ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.94268385898721614114129118899553876939587958136528806926922147261580827369696
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2466342864 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2466342864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.sram_ctrl_stress_all_with_rand_reset.81409182003431883406864024935138744427435684167770907986514014351010256317250
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2198365154 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2198365154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

1.sram_ctrl_stress_all.70495971409698110908946714006252972427585701443720832015102108362886298680938
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  19027829 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  19027829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.sram_ctrl_stress_all.41643058426913183650781282670883745678873645399225708192901509896653877104884
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 151378696 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 151378696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_executable has 1 failures.
  - 7.sram_ctrl_executable.84462400850893064742955269543576160582262016765906868292142196015419214762420
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 10403582716 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf8b96046
  UVM_INFO @ 10403582716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 24.sram_ctrl_stress_all.73107469641724146316157192520348909111647134787851602856960311793666233099428
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/24.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10279150124 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xbccfb032
  UVM_INFO @ 10279150124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 10.sram_ctrl_csr_mem_rw_with_rand_reset.63843514458496372696819238079301976798696053383223600848077894737767234074032
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  80995967 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  80995967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 17.sram_ctrl_regwen.104773743078257589524693436046839935037903084137555597315918950516679572082077
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 10297079877 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x1ad38005
  UVM_INFO @ 10297079877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 31.sram_ctrl_multiple_keys.26597253218644424818755134206832537825618958870751589414780295698271821126180
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/31.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 26270465648 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xeac4c7a3
  UVM_INFO @ 26270465648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```