SRAM_CTRL/RET Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.868m 3.179ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.700s 34.638us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 13.196us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.760s 1.825ms 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.710s 20.376us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.600s 85.199us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 13.196us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 20.376us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.720s 2.703ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.390s 256.916us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 38.269m 68.329ms 47 50 94.00
V2 stress_pipeline sram_ctrl_stress_pipeline 5.989m 13.630ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.355m 3.995ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 34.944m 82.178ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.490s 1.049ms 50 50 100.00
V2 executable sram_ctrl_executable 38.420m 29.471ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.579m 6.256ms 50 50 100.00
sram_ctrl_partial_access_b2b 10.649m 33.259ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.618m 538.853us 50 50 100.00
sram_ctrl_throughput_w_partial_write 3.126m 303.966us 50 50 100.00
V2 regwen sram_ctrl_regwen 28.324m 3.482ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.870s 55.136us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.214h 100.212ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.730s 67.213us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.490s 1.051ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.490s 1.051ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.700s 34.638us 5 5 100.00
sram_ctrl_csr_rw 0.710s 13.196us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 20.376us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 48.569us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.700s 34.638us 5 5 100.00
sram_ctrl_csr_rw 0.710s 13.196us 20 20 100.00
sram_ctrl_csr_aliasing 0.710s 20.376us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 48.569us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.230s 543.612us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
sram_ctrl_tl_intg_err 2.540s 277.310us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.540s 277.310us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 28.324m 3.482ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 13.196us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 38.420m 29.471ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 38.420m 29.471ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 38.420m 29.471ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.490s 1.049ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.230s 543.612us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.868m 3.179ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.868m 3.179ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.868m 3.179ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 38.420m 29.471ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.490s 1.049ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.868m 3.179ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.280s 1.634ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 14.124m 4.189ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 1031 1040 99.13

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 13 81.25
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results