SRAM_CTRL/RET Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: e439226b6c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 3.041m 673.165us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 25.054us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 25.037us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.260s 184.682us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.720s 45.757us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.380s 43.279us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 25.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 45.757us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.270s 5.195ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.750s 193.144us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 27.797m 3.843ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.174m 18.303ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.519m 5.600ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 37.364m 4.447ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 10.600s 3.686ms 50 50 100.00
V2 executable sram_ctrl_executable 30.439m 258.256ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.883m 10.420ms 49 50 98.00
sram_ctrl_partial_access_b2b 10.451m 185.791ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.745m 546.979us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.642m 1.308ms 50 50 100.00
V2 regwen sram_ctrl_regwen 35.585m 67.690ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.900s 343.947us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.490h 94.757ms 48 50 96.00
V2 alert_test sram_ctrl_alert_test 0.750s 14.771us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.890s 571.895us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.890s 571.895us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 25.054us 5 5 100.00
sram_ctrl_csr_rw 0.720s 25.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 45.757us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 80.258us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 25.054us 5 5 100.00
sram_ctrl_csr_rw 0.720s 25.037us 20 20 100.00
sram_ctrl_csr_aliasing 0.720s 45.757us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 80.258us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.610s 8.012ms 19 20 95.00
V2S tl_intg_err sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
sram_ctrl_tl_intg_err 2.570s 284.627us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.570s 284.627us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 35.585m 67.690ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 25.037us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 30.439m 258.256ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 30.439m 258.256ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 30.439m 258.256ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 10.600s 3.686ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.610s 8.012ms 19 20 95.00
V2S sec_cm_mem_readback sram_ctrl_smoke 3.041m 673.165us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 3.041m 673.165us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 3.041m 673.165us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 30.439m 258.256ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 10.600s 3.686ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 3.041m 673.165us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.480s 360.508us 5 5 100.00
V2S TOTAL 44 45 97.78
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 15.303m 5.514ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1026 1040 98.65

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 14 87.50
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results