SRAM_CTRL/RET Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 1.428m 467.274us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.690s 22.337us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 16.631us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.160s 509.602us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.790s 57.240us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.680s 155.259us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 16.631us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 57.240us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.250s 2.729ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.190s 374.719us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 35.093m 19.513ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 8.443m 23.114ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.558m 10.375ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 36.097m 4.645ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.920s 7.144ms 50 50 100.00
V2 executable sram_ctrl_executable 29.517m 17.410ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.487m 3.599ms 50 50 100.00
sram_ctrl_partial_access_b2b 9.255m 245.526ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.575m 912.061us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.592m 158.808us 50 50 100.00
V2 regwen sram_ctrl_regwen 36.312m 9.229ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.860s 43.341us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.656h 80.077ms 44 50 88.00
V2 alert_test sram_ctrl_alert_test 0.700s 25.692us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.110s 1.044ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.110s 1.044ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.690s 22.337us 5 5 100.00
sram_ctrl_csr_rw 0.720s 16.631us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 57.240us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 103.693us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.690s 22.337us 5 5 100.00
sram_ctrl_csr_rw 0.720s 16.631us 20 20 100.00
sram_ctrl_csr_aliasing 0.790s 57.240us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 103.693us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.740s 1.687ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
sram_ctrl_tl_intg_err 3.590s 2.543ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.590s 2.543ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 36.312m 9.229ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 16.631us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 29.517m 17.410ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 29.517m 17.410ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 29.517m 17.410ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.920s 7.144ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.740s 1.687ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 1.428m 467.274us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 1.428m 467.274us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 1.428m 467.274us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 29.517m 17.410ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.920s 7.144ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 1.428m 467.274us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.290s 289.601us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 19.766m 1.801ms 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results