SRAM_CTRL/RET Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.878m	2.658ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	39.517us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	96.484us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.340s	634.052us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	39.887us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.310s	40.560us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	96.484us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.887us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.530s	2.602ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.450s	2.741ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	37.320m	6.843ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.914m	17.292ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.366m	10.613ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.796m	5.710ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.790s	5.764ms	50	50	100.00
V2	executable	sram_ctrl_executable	32.078m	16.996ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.633m	1.511ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.950m	27.328ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.749m	143.232us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.494m	591.848us	50	50	100.00
V2	regwen	sram_ctrl_regwen	37.718m	3.281ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.850s	75.560us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.813h	257.857ms	48	50	96.00
V2	alert_test	sram_ctrl_alert_test	0.710s	86.810us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.940s	537.054us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.940s	537.054us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	39.517us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	96.484us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.887us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	89.741us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	39.517us	5	5	100.00
		sram_ctrl_csr_rw	0.690s	96.484us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	39.887us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	89.741us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.560s	1.667ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
		sram_ctrl_tl_intg_err	2.800s	2.276ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.800s	2.276ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	37.718m	3.281ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	96.484us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	32.078m	16.996ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	32.078m	16.996ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	32.078m	16.996ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.790s	5.764ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.560s	1.667ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.878m	2.658ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.878m	2.658ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.878m	2.658ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	32.078m	16.996ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.790s	5.764ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.878m	2.658ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.300s	945.038us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.354m	1.736ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 1.sram_ctrl_stress_all_with_rand_reset.54046328502226461770186009992273156070464796293814940086138123292720463201897
    Line 327, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4143508315 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4143508315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.sram_ctrl_stress_all_with_rand_reset.96470911774421039345789526324594482242345166744835762771034541480749328160114
    Line 387, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1293647111 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1293647111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

4.sram_ctrl_stress_all.22976471924084197809388620211616068934410350059482920177751251371902674969477
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 547817597 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 547817597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.sram_ctrl_stress_all.19726326667813358671778443319592445781361445262620132639843657126138050337687
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  74166165 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  74166165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.86862268695408796950818035023518321755205084233233600681941984264117606908558
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110478332 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 110478332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```