SRAM_CTRL/RET Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.536m	570.997us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.680s	13.575us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	37.157us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.410s	864.262us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.730s	60.606us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	11.190s	10.004ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	37.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	60.606us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.900s	2.488ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.970s	383.575us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	45.922m	30.732ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.981m	16.830ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.530m	20.326ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	41.307m	12.038ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.620s	3.204ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.673m	80.828ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.050m	222.589us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.560m	103.920ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.681m	140.541us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.536m	160.205us	50	50	100.00
V2	regwen	sram_ctrl_regwen	32.766m	16.226ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	62.175us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.638h	58.324ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.740s	45.179us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.790s	2.108ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.790s	2.108ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.680s	13.575us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	37.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	60.606us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	82.634us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.680s	13.575us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	37.157us	20	20	100.00
		sram_ctrl_csr_aliasing	0.730s	60.606us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.880s	82.634us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.200s	1.591ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
		sram_ctrl_tl_intg_err	3.600s	758.889us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.600s	758.889us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	32.766m	16.226ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	37.157us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.673m	80.828ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.673m	80.828ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.673m	80.828ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.620s	3.204ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.200s	1.591ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.536m	570.997us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.536m	570.997us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.536m	570.997us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.673m	80.828ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.620s	3.204ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.536m	570.997us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.080s	439.535us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	20.768m	13.117ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1023	1040	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	12	75.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 11.sram_ctrl_stress_all_with_rand_reset.97932185500385669242374244731234616566214194788768503479472232285641165340226
    Line 382, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3788333635 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3788333635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_stress_all_with_rand_reset.22400723320499242019229262253805716351042830346148511210965031523113609646514
    Line 321, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2617927873 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2617927873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 4 failures:

Test sram_ctrl_stress_all has 4 failures.

10.sram_ctrl_stress_all.93489249477341812479391450356891054189264061273878291074312777731954495565085
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  50222686 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  50222686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.sram_ctrl_stress_all.39538124743187099759441182917666022451281091692492514503612427854626506353870
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  88258345 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  88258345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 3.sram_ctrl_multiple_keys.93384960864610450079256308327708783495604787221363189101066751952873408900757
    Line 288, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 48717270160 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x64e59118
  UVM_INFO @ 48717270160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.7958806326891833387327907690460261045671587411932660011065718714061272535139
    Line 328, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2573575082 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2573575082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 10.sram_ctrl_executable.97390491023875222617790349970592448813615674739141052600481315707215763746889
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 64305699329 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xf0b60c54
  UVM_INFO @ 64305699329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:267) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 14.sram_ctrl_regwen.95427039445729378361228356242526717226560036107694863865515893244576811415741
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 16229015114 ps: (cip_base_vseq.sv:267) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x3bf81c02
  UVM_INFO @ 16229015114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.3981406178301666793379840945669501341422864033609220165518325697815926585041
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10003905815 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10003905815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 16.sram_ctrl_stress_all.112237722914255228457999700279139467365638428334919960128002200954700978232998
    Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 2603775368 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0xbf [10111111] vs 0x73 [1110011]) addr 0x6d894734 read out mismatch
  UVM_INFO @ 2603775368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 48.sram_ctrl_stress_all.106804247121405820247441467438671957119487395403963184138753228050595581860616
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/48.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 119477938 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 119477938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```