SRAM_CTRL/RET Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.607m 1.485ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.710s 14.776us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.730s 22.943us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.430s 174.308us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.760s 85.925us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.900s 43.312us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.730s 22.943us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 85.925us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.390s 2.965ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.300s 1.723ms 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 31.705m 21.481ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.463m 8.384ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.473m 86.121ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 35.461m 5.404ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.760s 717.812us 50 50 100.00
V2 executable sram_ctrl_executable 26.970m 26.057ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.538m 3.015ms 50 50 100.00
sram_ctrl_partial_access_b2b 11.317m 473.278ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.457m 138.706us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.491m 613.864us 50 50 100.00
V2 regwen sram_ctrl_regwen 23.825m 3.533ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.840s 30.730us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.796h 64.491ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.700s 28.975us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.380s 566.229us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.380s 566.229us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.710s 14.776us 5 5 100.00
sram_ctrl_csr_rw 0.730s 22.943us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 85.925us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 108.240us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.710s 14.776us 5 5 100.00
sram_ctrl_csr_rw 0.730s 22.943us 20 20 100.00
sram_ctrl_csr_aliasing 0.760s 85.925us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.880s 108.240us 20 20 100.00
V2 TOTAL 735 740 99.32
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.430s 664.017us 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
sram_ctrl_tl_intg_err 2.850s 1.380ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.850s 1.380ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 23.825m 3.533ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.730s 22.943us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 26.970m 26.057ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 26.970m 26.057ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 26.970m 26.057ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.760s 717.812us 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.430s 664.017us 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.607m 1.485ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.607m 1.485ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.607m 1.485ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 26.970m 26.057ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.760s 717.812us 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.607m 1.485ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.160s 1.049ms 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 16.802m 19.170ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1030 1040 99.04

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results