SRAM_CTRL/RET Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.623m 269.323us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.790s 202.409us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 132.230us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.470s 634.195us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.740s 38.712us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.620s 77.498us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 132.230us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 38.712us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.500s 1.761ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.940s 176.126us 50 50 100.00
V1 TOTAL 204 205 99.51
V2 multiple_keys sram_ctrl_multiple_keys 31.143m 10.381ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.810m 8.157ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.488m 21.579ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 29.656m 14.915ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.380s 2.200ms 50 50 100.00
V2 executable sram_ctrl_executable 42.832m 140.219ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.659m 251.093us 50 50 100.00
sram_ctrl_partial_access_b2b 9.879m 123.961ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.474m 863.888us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.608m 158.329us 50 50 100.00
V2 regwen sram_ctrl_regwen 33.503m 14.711ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.840s 44.102us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.440h 25.960ms 47 50 94.00
V2 alert_test sram_ctrl_alert_test 0.700s 152.503us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.120s 830.556us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.120s 830.556us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.790s 202.409us 5 5 100.00
sram_ctrl_csr_rw 0.720s 132.230us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 38.712us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 288.480us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.790s 202.409us 5 5 100.00
sram_ctrl_csr_rw 0.720s 132.230us 20 20 100.00
sram_ctrl_csr_aliasing 0.740s 38.712us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.850s 288.480us 20 20 100.00
V2 TOTAL 737 740 99.59
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 6.150s 1.573ms 19 20 95.00
V2S tl_intg_err sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
sram_ctrl_tl_intg_err 3.140s 1.928ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.140s 1.928ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 33.503m 14.711ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 132.230us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 42.832m 140.219ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 42.832m 140.219ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 42.832m 140.219ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.380s 2.200ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 6.150s 1.573ms 19 20 95.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.623m 269.323us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.623m 269.323us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.623m 269.323us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 42.832m 140.219ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.380s 2.200ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.623m 269.323us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.280s 288.021us 5 5 100.00
V2S TOTAL 44 45 97.78
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.587m 12.291ms 45 50 90.00
V3 TOTAL 45 50 90.00
TOTAL 1030 1040 99.04

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26

Failure Buckets

Past Results