SRAM_CTRL/RET Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.241m	571.480us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	86.221us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	40.887us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.330s	355.587us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.720s	19.068us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.970s	10.020ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	40.887us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.068us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	11.590s	3.632ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.930s	1.019ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	23.930m	9.150ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.806m	19.135ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.412m	35.530ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.622m	8.853ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.610s	5.269ms	50	50	100.00
V2	executable	sram_ctrl_executable	39.424m	108.928ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.713m	1.268ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.230m	101.870ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.537m	922.984us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.469m	148.381us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.055m	7.387ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.860s	34.830us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.072h	41.559ms	43	50	86.00
V2	alert_test	sram_ctrl_alert_test	0.730s	95.111us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.200s	567.266us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.200s	567.266us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	86.221us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	40.887us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.068us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	145.853us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	86.221us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	40.887us	20	20	100.00
		sram_ctrl_csr_aliasing	0.720s	19.068us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	145.853us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.520s	6.309ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
		sram_ctrl_tl_intg_err	4.040s	4.017ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.040s	4.017ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.055m	7.387ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	40.887us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	39.424m	108.928ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	39.424m	108.928ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	39.424m	108.928ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.610s	5.269ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.520s	6.309ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.241m	571.480us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.241m	571.480us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.241m	571.480us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	39.424m	108.928ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.610s	5.269ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.241m	571.480us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.230s	815.861us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	15.467m	12.225ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 8 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.113043311108108961183039900388296900464598483720753475952711876934289780358307
    Line 309, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 732460797 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 732460797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.sram_ctrl_stress_all_with_rand_reset.71523947200612718135522695167958625776496186081569318840654358494903386656834
    Line 286, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2464608074 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2464608074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 6 failures:

Test sram_ctrl_stress_all has 6 failures.

14.sram_ctrl_stress_all.70371033060088469924884205557368902447575928021734992618941348149581268490301
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 241829432 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 241829432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.sram_ctrl_stress_all.64479052020640257900190267558339233930878406212653942675679015092663987919583
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 773997408 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 773997408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 12.sram_ctrl_multiple_keys.701137110297884114873418625922006283064997430677950464773980957604321999573
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/12.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10288111967 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x2c07197a
  UVM_INFO @ 10288111967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 42.sram_ctrl_stress_all.58421459361482331828508927793914919820194303525090085733909256741058082117957
    Line 292, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 111527926327 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x5865e471
  UVM_INFO @ 111527926327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 4.sram_ctrl_csr_mem_rw_with_rand_reset.88061887969921358538699130343845309035204216519651645242014872514278677100742
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  81126043 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  81126043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.5279081083063048997153458372812812716129560796377092711814204235631318387446
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10019913510 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10019913510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```