SRAM_CTRL/RET Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.551m	185.254us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.700s	19.140us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.710s	111.458us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.920s	111.427us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	36.324us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.170s	130.861us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.710s	111.458us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.324us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.680s	1.279ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.900s	734.921us	50	50	100.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	26.227m	102.821ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.606m	8.553ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.343m	4.331ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.402m	10.668ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.310s	10.158ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.470m	15.161ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.812m	1.386ms	50	50	100.00
		sram_ctrl_partial_access_b2b	11.930m	33.848ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.993m	517.889us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.468m	320.428us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.236m	26.781ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.830s	253.808us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.833h	153.147ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.730s	14.256us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.290s	2.251ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.290s	2.251ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.700s	19.140us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	111.458us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.324us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	69.449us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.700s	19.140us	5	5	100.00
		sram_ctrl_csr_rw	0.710s	111.458us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	36.324us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	69.449us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.290s	954.357us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
		sram_ctrl_tl_intg_err	2.710s	1.697ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.710s	1.697ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.236m	26.781ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.710s	111.458us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.470m	15.161ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.470m	15.161ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.470m	15.161ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.310s	10.158ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.290s	954.357us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.551m	185.254us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.551m	185.254us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.551m	185.254us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.470m	15.161ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.310s	10.158ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.551m	185.254us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.450s	974.023us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.639m	32.824ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1019	1040	97.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 10 failures.
  - 13.sram_ctrl_stress_all_with_rand_reset.97878496227506380813237442099033770170514412726625960734766443051619173218635
    Line 377, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5495687830 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5495687830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.sram_ctrl_stress_all_with_rand_reset.64675808594561719775776808865413803782954660458688574468354827819895264260604
    Line 306, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 737215519 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 737215519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

13.sram_ctrl_stress_all.2363817171129416271690227887017844945717852531284338133137137782835700513933
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  37439880 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  37439880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sram_ctrl_stress_all.60040936112826370623178047652151620688933124087586187763207814197803147070371
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  34736517 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  34736517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.46519405414761855880332922053553220826504593429957635860417296071922342417668
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22278498 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  22278498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.10972174083833357709532297348601973809886462026446250573158492113445636518167
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112851494 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @ 112851494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 5.sram_ctrl_csr_mem_rw_with_rand_reset.100969101942095615233848791136392992493116837029979915543817990175251991406248
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  25090769 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  25090769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.41973897677618388666880211238671684082806477411800234905632294181204355075948
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  29023522 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  29023522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_regwen has 1 failures.
  - 35.sram_ctrl_regwen.93452717182573553435978747269155221143689536940861913054483168404460108629679
    Line 296, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 67475109981 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x90011afd
  UVM_INFO @ 67475109981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 42.sram_ctrl_stress_all.29165930076739134178771071781710977610344476291795615614095146877733513218325
    Line 331, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/42.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 168728088594 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x7b6a60a4
  UVM_INFO @ 168728088594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```