SRAM_CTRL/RET Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: bbf435ceff

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.527m 631.171us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.680s 22.377us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.720s 35.948us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.060s 445.837us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.750s 15.018us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.600s 60.404us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.720s 35.948us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 15.018us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.880s 8.104ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.300s 382.789us 50 50 100.00
V1 TOTAL 205 205 100.00
V2 multiple_keys sram_ctrl_multiple_keys 39.965m 86.917ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.273m 9.020ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.447m 22.424ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.089m 4.327ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 9.820s 4.580ms 50 50 100.00
V2 executable sram_ctrl_executable 27.738m 13.788ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.401m 772.970us 50 50 100.00
sram_ctrl_partial_access_b2b 11.296m 180.953ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.521m 510.151us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.681m 781.211us 50 50 100.00
V2 regwen sram_ctrl_regwen 32.883m 35.814ms 49 50 98.00
V2 ram_cfg sram_ctrl_ram_cfg 0.870s 62.470us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 2.400h 102.464ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.740s 27.643us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.270s 169.526us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.270s 169.526us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.680s 22.377us 5 5 100.00
sram_ctrl_csr_rw 0.720s 35.948us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 15.018us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 178.906us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.680s 22.377us 5 5 100.00
sram_ctrl_csr_rw 0.720s 35.948us 20 20 100.00
sram_ctrl_csr_aliasing 0.750s 15.018us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.840s 178.906us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.690s 1.684ms 19 20 95.00
V2S tl_intg_err sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
sram_ctrl_tl_intg_err 2.670s 1.139ms 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.670s 1.139ms 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 32.883m 35.814ms 49 50 98.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.720s 35.948us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 27.738m 13.788ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 27.738m 13.788ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 27.738m 13.788ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 9.820s 4.580ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.690s 1.684ms 19 20 95.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.527m 631.171us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.527m 631.171us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.527m 631.171us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 27.738m 13.788ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 9.820s 4.580ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.527m 631.171us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.410s 273.030us 5 5 100.00
V2S TOTAL 44 45 97.78
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 17.841m 7.672ms 39 50 78.00
V3 TOTAL 39 50 78.00
TOTAL 1021 1040 98.17

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 16 16 13 81.25
V2S 3 3 2 66.67
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results