SRAM_CTRL/RET Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.374m	648.754us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	47.671us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	15.817us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	976.405us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	67.481us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.860s	169.338us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	15.817us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	67.481us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	12.130s	2.848ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.510s	1.891ms	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	39.988m	23.549ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.550m	16.147ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.423m	10.186ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.546m	2.919ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.080s	2.699ms	50	50	100.00
V2	executable	sram_ctrl_executable	40.500m	20.855ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.398m	231.712us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.067m	106.112ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.488m	544.169us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.636m	309.071us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.148m	7.335ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.890s	74.880us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.014h	54.616ms	41	50	82.00
V2	alert_test	sram_ctrl_alert_test	0.750s	161.893us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.940s	972.980us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.940s	972.980us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	47.671us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.817us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	67.481us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	26.947us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	47.671us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	15.817us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	67.481us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	26.947us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.670s	4.028ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
		sram_ctrl_tl_intg_err	2.610s	2.213ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.610s	2.213ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.148m	7.335ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	15.817us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	40.500m	20.855ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	40.500m	20.855ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	40.500m	20.855ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.080s	2.699ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.670s	4.028ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.374m	648.754us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.374m	648.754us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.374m	648.754us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	40.500m	20.855ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.080s	2.699ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.374m	648.754us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.070s	516.441us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.537m	15.946ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	15	93.75
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 13.sram_ctrl_stress_all_with_rand_reset.46081977816770681391984338035022792149359247674390079431620772997893926316914
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 611865132 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 611865132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.sram_ctrl_stress_all_with_rand_reset.18905259762493982217857408309585931300505496607411190602376277689163855878247
    Line 379, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 998546071 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 998546071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 5 failures:

Test sram_ctrl_stress_all has 5 failures.

14.sram_ctrl_stress_all.34713120790206045165975469471639749133534740318415754476708421773142741127171
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  57688246 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  57688246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.sram_ctrl_stress_all.96048768382559845243666237171835632375477790129183832697927776607676285165625
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 123192916 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 123192916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 9.sram_ctrl_stress_all.50487960049425374956733919564010179817351515434872506100743906349434373616444
    Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 159579875229 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x4e4cfb2a
  UVM_INFO @ 159579875229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.sram_ctrl_stress_all.2899906907191059934878447863166242130988136817810337996085020185619485697008
    Line 298, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 97477041476 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x954e4985
  UVM_INFO @ 97477041476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.18108902079420567177344898648585069726458078394203775615891210895875304927783
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46516252 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (10 [0xa] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  46516252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 34.sram_ctrl_stress_all.75174872350077330606323594266147642679373094736826930286057446669864977940215
    Line 304, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 85495275449 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xfa012913
  UVM_INFO @ 85495275449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 36.sram_ctrl_stress_all.24505848548957112560312261902484610565705739224674622845082061928690043334411
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  23142686 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  23142686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```