5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.561m | 289.522us | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 0.700s | 17.691us | 4 | 5 | 80.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 0.710s | 19.700us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.320s | 1.171ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 0.750s | 78.454us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 2.640s | 132.611us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 0.710s | 19.700us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 0.750s | 78.454us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 12.390s | 2.597ms | 50 | 50 | 100.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 7.190s | 3.465ms | 50 | 50 | 100.00 |
| V1 | TOTAL | 202 | 205 | 98.54 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 32.349m | 4.735ms | 49 | 50 | 98.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.445m | 4.319ms | 50 | 50 | 100.00 |
| V2 | bijection | sram_ctrl_bijection | 1.515m | 5.994ms | 50 | 50 | 100.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 30.836m | 17.200ms | 50 | 50 | 100.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 10.690s | 3.264ms | 50 | 50 | 100.00 |
| V2 | executable | sram_ctrl_executable | 34.924m | 15.641ms | 50 | 50 | 100.00 |
| V2 | partial_access | sram_ctrl_partial_access | 2.350m | 388.335us | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 8.854m | 239.536ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 2.671m | 1.180ms | 50 | 50 | 100.00 |
| sram_ctrl_throughput_w_partial_write | 2.538m | 159.224us | 50 | 50 | 100.00 | ||
| V2 | regwen | sram_ctrl_regwen | 30.552m | 13.839ms | 50 | 50 | 100.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 0.860s | 28.503us | 50 | 50 | 100.00 |
| V2 | stress_all | sram_ctrl_stress_all | 1.329h | 125.022ms | 41 | 50 | 82.00 |
| V2 | alert_test | sram_ctrl_alert_test | 0.710s | 33.303us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 4.870s | 522.392us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 4.870s | 522.392us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 0.700s | 17.691us | 4 | 5 | 80.00 |
| sram_ctrl_csr_rw | 0.710s | 19.700us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 78.454us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 77.097us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 0.700s | 17.691us | 4 | 5 | 80.00 |
| sram_ctrl_csr_rw | 0.710s | 19.700us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 0.750s | 78.454us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 0.830s | 77.097us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 730 | 740 | 98.65 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 4.050s | 828.973us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 2.550s | 243.079us | 19 | 20 | 95.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 2.550s | 243.079us | 19 | 20 | 95.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 30.552m | 13.839ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 0.710s | 19.700us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 34.924m | 15.641ms | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 34.924m | 15.641ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 34.924m | 15.641ms | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 10.690s | 3.264ms | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 4.050s | 828.973us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.561m | 289.522us | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.561m | 289.522us | 49 | 50 | 98.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.561m | 289.522us | 49 | 50 | 98.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 34.924m | 15.641ms | 50 | 50 | 100.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 10.690s | 3.264ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.561m | 289.522us | 49 | 50 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.190s | 1.952ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 44 | 45 | 97.78 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 19.901m | 10.762ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 1020 | 1040 | 98.08 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 5 | 62.50 |
| V2 | 16 | 16 | 14 | 87.50 |
| V2S | 3 | 3 | 2 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 9 failures:
0.sram_ctrl_stress_all.23480601861630249944848587296163015606630059127204753991261870465109658820928
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 78003364 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 78003364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.sram_ctrl_stress_all.94071461829564934845865786175301605981031647613392704895879598805134938215430
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
UVM_ERROR @ 218380442 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
UVM_INFO @ 218380442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (cip_base_vseq.sv:836) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
16.sram_ctrl_stress_all_with_rand_reset.54587492552633034087391491814038002306549874685188711435087349044217152802145
Line 297, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 653786633 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 653786633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.sram_ctrl_stress_all_with_rand_reset.16918350293300352181565692682838392425650351269957196592901177409537896981196
Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/30.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2310640871 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2310640871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 2 failures:
Test sram_ctrl_smoke has 1 failures.
9.sram_ctrl_smoke.561376575842307287012125534461858175731677708699492032500725353269686404733
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_smoke/latest/run.log
UVM_FATAL @ 10284729583 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xf8942bb3
UVM_INFO @ 10284729583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
19.sram_ctrl_stress_all_with_rand_reset.103421282480229083097708210711362524693205292552904279260818479333998913252371
Line 421, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 22008087073 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x91caffc4
UVM_INFO @ 22008087073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((pend_req[*].pend == *'b0) || $test$plusargs("disable_assert_final_checks"))' has 1 failures:
4.sram_ctrl_csr_hw_reset.106772803244231047738552759643351664921485396947763109070681409903195112822219
Line 314, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest/run.log
Offending '((pend_req[242].pend == 1'b0) || $test$plusargs("disable_assert_final_checks"))'
UVM_ERROR @ 17690694 ps: (tlul_assert.sv:301) [ASSERT FAILED] noOutstandingReqsAtEndOfSim_A
UVM_INFO @ 17690694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
14.sram_ctrl_csr_mem_rw_with_rand_reset.9566952335476492872880368537700655662845728334493134800239232402886500844921
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 82027158 ps: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 82027158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:264) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
16.sram_ctrl_multiple_keys.45350742366160984429229120239654561075316428040781334847902891182743281436522
Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_multiple_keys/latest/run.log
UVM_FATAL @ 10541950229 ps: (cip_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x42eefd81
UVM_INFO @ 10541950229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
16.sram_ctrl_tl_intg_err.52244424172853606639907107431252579826253672607927078851715382041552928943968
Line 381, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/16.sram_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 546117031 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 546117031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:755) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
25.sram_ctrl_stress_all_with_rand_reset.694851459574815357170557445575687034946551533162637010302161044558994288555
Line 291, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/25.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43688197 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 43688197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---