SRAM_CTRL/RET Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.659m 722.932us 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 27.829us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.760s 127.705us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.420s 158.869us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.770s 51.792us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.060s 65.152us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.760s 127.705us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 51.792us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 12.290s 2.325ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 6.250s 403.172us 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 27.701m 105.399ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 6.481m 4.004ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.633m 64.847ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 31.426m 5.526ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 12.540s 1.182ms 50 50 100.00
V2 executable sram_ctrl_executable 26.695m 3.150ms 50 50 100.00
V2 partial_access sram_ctrl_partial_access 2.724m 658.766us 50 50 100.00
sram_ctrl_partial_access_b2b 9.529m 24.589ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.515m 135.605us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.886m 163.993us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.955m 105.350ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.920s 42.840us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.826h 75.549ms 43 50 86.00
V2 alert_test sram_ctrl_alert_test 0.720s 97.290us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.710s 264.552us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.710s 264.552us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 27.829us 5 5 100.00
sram_ctrl_csr_rw 0.760s 127.705us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 51.792us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 34.608us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 27.829us 5 5 100.00
sram_ctrl_csr_rw 0.760s 127.705us 20 20 100.00
sram_ctrl_csr_aliasing 0.770s 51.792us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 34.608us 20 20 100.00
V2 TOTAL 733 740 99.05
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.540s 2.744ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
sram_ctrl_tl_intg_err 3.680s 819.516us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 3.680s 819.516us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.955m 105.350ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.760s 127.705us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 26.695m 3.150ms 50 50 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 26.695m 3.150ms 50 50 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 26.695m 3.150ms 50 50 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 12.540s 1.182ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.540s 2.744ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.659m 722.932us 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.659m 722.932us 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.659m 722.932us 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 26.695m 3.150ms 50 50 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 12.540s 1.182ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.659m 722.932us 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.050s 617.687us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 10.107m 3.637ms 47 50 94.00
V3 TOTAL 47 50 94.00
TOTAL 1028 1040 98.85

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 15 93.75
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 99.16 94.27 99.72 100.00 95.95 99.12 97.26

Failure Buckets

Past Results