SRAM_CTRL/RET Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.944m	735.749us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.710s	32.586us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	14.028us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	576.933us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	21.997us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.040s	10.008ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	14.028us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.997us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.030s	5.028ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.800s	1.705ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	29.166m	257.168ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.426m	9.079ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.549m	21.552ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	27.372m	21.472ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.270s	1.756ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.786m	165.037ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.691m	2.589ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.231m	100.887ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.473m	513.648us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.657m	601.560us	50	50	100.00
V2	regwen	sram_ctrl_regwen	36.730m	116.848ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.880s	216.301us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.741h	13.648ms	44	50	88.00
V2	alert_test	sram_ctrl_alert_test	0.710s	35.873us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.070s	251.361us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.070s	251.361us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.710s	32.586us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	14.028us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.997us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	20.620us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.710s	32.586us	5	5	100.00
		sram_ctrl_csr_rw	0.700s	14.028us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	21.997us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.810s	20.620us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.790s	1.375ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
		sram_ctrl_tl_intg_err	2.580s	664.589us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.580s	664.589us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	36.730m	116.848ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	14.028us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.786m	165.037ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.786m	165.037ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.786m	165.037ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.270s	1.756ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.790s	1.375ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.944m	735.749us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.944m	735.749us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.944m	735.749us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.786m	165.037ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.270s	1.756ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.944m	735.749us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.420s	542.915us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.712m	15.386ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1029	1040	98.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Failure Buckets

Offending '(!$isunknown(rdata_o))' has 3 failures:
- Test sram_ctrl_stress_all has 3 failures.
  - 4.sram_ctrl_stress_all.110501661940263261145022442685478571575131027092693467271106045245578662997215
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @  50851367 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  50851367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 11.sram_ctrl_stress_all.36403271033997832750150484482025395807263289941699851969690990053982529206839
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 651191001 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 651191001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

26.sram_ctrl_stress_all.100296525618688974276350978480560163441485306877113933082119994148842477196192
Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 148207937 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 148207937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

36.sram_ctrl_stress_all.83673833096852366403431882945766520839051653680895352920709318865079237185850
Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/36.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 1127869909 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 1127869909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:848) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 43.sram_ctrl_stress_all_with_rand_reset.41550559895724371715786009623677883685849576400252125986530956319351016089621
    Line 581, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/43.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1381196853 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1381196853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 47.sram_ctrl_stress_all_with_rand_reset.76834689213228572342017488145346117026518706818170478649510629222646339203178
    Line 348, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2815914289 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2815914289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:149) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.sram_ctrl_csr_mem_rw_with_rand_reset.104666903610808087208548018108548868423197709678200437279539628101199904834195
    Line 270, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10007754866 ps: (sram_ctrl_base_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10007754866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 4.sram_ctrl_multiple_keys.70321060573590170769181086459806467782402358819329110343953018049960765560060
    Line 276, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/4.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 20857964061 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x8f0f3506
  UVM_INFO @ 20857964061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.13841764476056043123050346134869945744503171792192435822266007792897558055336
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 101779532 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 101779532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 18.sram_ctrl_stress_all.69783456330378584152599584032663146652585181421581555446706848817232465598029
    Line 371, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 3862556179 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0x31 [110001] vs 0x93 [10010011]) addr 0x477eb0b4 read out mismatch
  UVM_INFO @ 3862556179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```