SRAM_CTRL/RET Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.850m	163.774us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	18.407us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	47.784us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.950s	42.394us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.760s	149.067us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.050s	181.486us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	47.784us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	149.067us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.080s	6.543ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.070s	1.249ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.095m	12.755ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.322m	16.386ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.383m	17.187ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	29.260m	9.304ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.290s	3.917ms	50	50	100.00
V2	executable	sram_ctrl_executable	27.883m	37.411ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.449m	10.387ms	49	50	98.00
		sram_ctrl_partial_access_b2b	12.168m	114.438ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.755m	133.439us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.791m	310.428us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.626m	14.378ms	49	50	98.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.890s	64.101us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.791h	163.637ms	40	50	80.00
V2	alert_test	sram_ctrl_alert_test	0.730s	83.048us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.640s	862.283us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.640s	862.283us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	18.407us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	47.784us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	149.067us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	66.724us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	18.407us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	47.784us	20	20	100.00
		sram_ctrl_csr_aliasing	0.760s	149.067us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	66.724us	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.350s	812.428us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
		sram_ctrl_tl_intg_err	2.560s	296.658us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.560s	296.658us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.626m	14.378ms	49	50	98.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	47.784us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	27.883m	37.411ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	27.883m	37.411ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	27.883m	37.411ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.290s	3.917ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.350s	812.428us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.850m	163.774us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.850m	163.774us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.850m	163.774us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	27.883m	37.411ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.290s	3.917ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.850m	163.774us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.400s	618.272us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.660m	4.546ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1022	1040	98.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 7 failures:

Test sram_ctrl_stress_all has 7 failures.

6.sram_ctrl_stress_all.35224758176197880338470506112886747465595802358789480113438421767953323524210
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 103458606 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 103458606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.sram_ctrl_stress_all.27497875241265152720553238078357739859666602369698232952910754279369855484624
Line 273, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  22233361 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  22233361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 10.sram_ctrl_stress_all_with_rand_reset.57767781296234763318313024144444389193946661311216695723079745359785355417250
    Line 663, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1600895249 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1600895249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_stress_all_with_rand_reset.40336721710006616037003856043475483251141678938144014380584865401828874611042
    Line 512, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3917574622 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3917574622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 9.sram_ctrl_stress_all.83227426038725676523254844975233280828865015692315206124058540571590140727611
    Line 448, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 543900371625 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xcaec95a4
  UVM_INFO @ 543900371625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_regwen has 1 failures.
  - 14.sram_ctrl_regwen.63599742222023011295865605191764570367204363216727874895315370775907654858389
    Line 283, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 51405931175 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x24d30d2b
  UVM_INFO @ 51405931175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 2 failures:
- Test sram_ctrl_stress_all has 2 failures.
  - 26.sram_ctrl_stress_all.53786387165321452622616096633694216014587039041772251844802385590231339664097
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/26.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 364685327 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 364685327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 35.sram_ctrl_stress_all.83657030231478110672076673519052097109252315815710811323879286716466883151294
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_stress_all/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 286963560 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 286963560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_partial_access has 1 failures.
  - 32.sram_ctrl_partial_access.28323463920539114137380368049573622637830094153350159809651026996255366850429
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_partial_access/latest/run.log
```
  UVM_FATAL @ 10387198831 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x4f2e385c
  UVM_INFO @ 10387198831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```