SRAM_CTRL/RET Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.735m	6.303ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	14.528us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.730s	12.560us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.290s	367.764us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.740s	59.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.330s	86.910us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.730s	12.560us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.363us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.560s	9.419ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.950s	2.055ms	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	38.159m	5.287ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.474m	4.537ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.369m	16.552ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	38.433m	8.720ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.290s	2.000ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.823m	120.026ms	48	50	96.00
V2	partial_access	sram_ctrl_partial_access	2.538m	5.395ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.014m	145.485ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.692m	576.749us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.831m	295.037us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.553m	16.137ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.840s	98.089us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.145h	178.570ms	46	50	92.00
V2	alert_test	sram_ctrl_alert_test	0.710s	13.834us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.020s	1.062ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.020s	1.062ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	14.528us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	12.560us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.363us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	22.810us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	14.528us	5	5	100.00
		sram_ctrl_csr_rw	0.730s	12.560us	20	20	100.00
		sram_ctrl_csr_aliasing	0.740s	59.363us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.820s	22.810us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.810s	3.575ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
		sram_ctrl_tl_intg_err	3.020s	437.752us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.020s	437.752us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.553m	16.137ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.730s	12.560us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.823m	120.026ms	48	50	96.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.823m	120.026ms	48	50	96.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.823m	120.026ms	48	50	96.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.290s	2.000ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.810s	3.575ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.735m	6.303ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.735m	6.303ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.735m	6.303ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.823m	120.026ms	48	50	96.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.290s	2.000ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.735m	6.303ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.520s	918.464us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.433m	11.477ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			1024	1040	98.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	99.16	94.27	99.72	100.00	95.95	99.12	97.26

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 11.sram_ctrl_stress_all_with_rand_reset.10795380807371230151979325997953259424072831298520920023676449603273061615623
    Line 317, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/11.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2878352314 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2878352314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.sram_ctrl_stress_all_with_rand_reset.64215417443309963267703758839187330274304657539455407408955464291556613606981
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2475383057 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2475383057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_executable has 2 failures.
  - 22.sram_ctrl_executable.52576313805447458006974271060611300669419662756803551232166745916615596740058
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 23794047978 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa5cedde7
  UVM_INFO @ 23794047978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.sram_ctrl_executable.109988980393264071353842802052272032734722929508512598379522983555888521795776
    Line 290, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 54887299881 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa2118897
  UVM_INFO @ 54887299881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_stress_all has 1 failures.
  - 37.sram_ctrl_stress_all.49178964808674397799622720225124834504934936270583473198439814733231413887665
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/37.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 99075983645 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x2739d363
  UVM_INFO @ 99075983645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 2 failures:

Test sram_ctrl_stress_all has 2 failures.

0.sram_ctrl_stress_all.87131767164889541031507831665266247370897181003885516134627202591663172435471
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  68961555 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  68961555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.sram_ctrl_stress_all.48730979071291605750539305783093002919454975812948608660448908357739099344720
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/18.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 460771147 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 460771147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.11437391763949623903198255694752634222954080333995077233279064812187600964467
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  96953433 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  96953433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.48592012774214189042699558851333079277805190534128805222574707219468683578776
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  94993669 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  94993669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 13.sram_ctrl_stress_all.94311675540073417668205841232623058454199441334571684462851536554279163159688
    Line 315, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 143929971375 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xf394eac5
  UVM_INFO @ 143929971375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.10431655403319386515641495906652524998796764671291117484685395872618267424483
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  44736968 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  44736968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```