SRAM_CTRL/RET Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.031m	124.441us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.830s	43.770us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	17.615us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.750s	43.851us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	48.447us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.760s	59.426us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	17.615us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	48.447us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.140s	2.626ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.450s	1.628ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	31.437m	148.945ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.477m	20.191ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.455m	5.353ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	30.803m	8.483ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	10.990s	1.127ms	50	50	100.00
V2	executable	sram_ctrl_executable	35.315m	4.861ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	2.460m	2.837ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.777m	143.776ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.602m	139.247us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.327m	152.290us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.916m	26.432ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	44.845us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.672h	61.234ms	41	50	82.00
V2	alert_test	sram_ctrl_alert_test	0.770s	42.193us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.500s	361.519us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.500s	361.519us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.830s	43.770us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	17.615us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	48.447us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	37.825us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.830s	43.770us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	17.615us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	48.447us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.830s	37.825us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.830s	1.191ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
		sram_ctrl_tl_intg_err	2.670s	2.769ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.670s	2.769ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.916m	26.432ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	17.615us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	35.315m	4.861ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	35.315m	4.861ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	35.315m	4.861ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	10.990s	1.127ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.830s	1.191ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.031m	124.441us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.031m	124.441us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.031m	124.441us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	35.315m	4.861ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	10.990s	1.127ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.031m	124.441us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.500s	587.546us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.585m	3.150ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1021	1040	98.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.95	99.16	94.27	99.72	100.00	95.95	99.12	97.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 7.sram_ctrl_stress_all_with_rand_reset.64783862792394443027720318048586194340967040277644806929468120313070955137773
    Line 452, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3722832943 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3722832943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.sram_ctrl_stress_all_with_rand_reset.46189534975069828630942289459200933004053828943026495163803545475225874824354
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2343450989 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2343450989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 7 failures:

Test sram_ctrl_stress_all has 7 failures.

17.sram_ctrl_stress_all.97257239286868301468217178241276580671240653808806157032215440497433378804026
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/17.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 246008382 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 246008382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.sram_ctrl_stress_all.84361563089312941300854281253157477684759317173629984875894948419870584688584
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/22.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @ 145398116 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @ 145398116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 23.sram_ctrl_executable.21673382676864853443239686431339956781495314995233423661794746450548973818589
    Line 284, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/23.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 37058983904 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x34e2a73f
  UVM_INFO @ 37058983904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 38.sram_ctrl_stress_all.60286524254113825678860415418233436694807216563960682801347847486191849851924
    Line 349, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 215684477717 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xbe4817a1
  UVM_INFO @ 215684477717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 44.sram_ctrl_stress_all.7937274780453509039829686341436374152800129067487697601944118429494845898029
    Line 346, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 397971473938 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xc98bb2af
  UVM_INFO @ 397971473938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```