SRAM_CTRL/RET Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.977m	669.915us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.740s	40.774us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.720s	23.540us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.070s	124.936us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	22.838us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.080s	41.440us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.720s	23.540us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.838us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.200s	4.096ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.570s	650.096us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	31.182m	22.786ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.581m	12.602ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.541m	11.032ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.772m	8.446ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	9.610s	3.295ms	50	50	100.00
V2	executable	sram_ctrl_executable	31.591m	16.758ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.924m	8.085ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.111m	23.566ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.958m	148.866us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	2.621m	621.031us	50	50	100.00
V2	regwen	sram_ctrl_regwen	25.595m	42.878ms	47	50	94.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.900s	66.129us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.604h	93.789ms	47	50	94.00
V2	alert_test	sram_ctrl_alert_test	0.740s	22.344us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.950s	635.055us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.950s	635.055us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.740s	40.774us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	23.540us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.838us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	26.531us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.740s	40.774us	5	5	100.00
		sram_ctrl_csr_rw	0.720s	23.540us	20	20	100.00
		sram_ctrl_csr_aliasing	0.750s	22.838us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.840s	26.531us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.480s	5.203ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
		sram_ctrl_tl_intg_err	3.200s	645.375us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.200s	645.375us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	25.595m	42.878ms	47	50	94.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.720s	23.540us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.591m	16.758ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.591m	16.758ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.591m	16.758ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	9.610s	3.295ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.480s	5.203ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.977m	669.915us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.977m	669.915us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.977m	669.915us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.591m	16.758ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	9.610s	3.295ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.977m	669.915us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.260s	276.378us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.265m	3.038ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1021	1040	98.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.98	99.16	94.27	99.72	100.00	95.95	99.12	97.62

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 7 failures.
  - 5.sram_ctrl_stress_all_with_rand_reset.16879130636138410188968990726633185883989601894394666329772936184536167416134
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1264392682 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1264392682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.sram_ctrl_stress_all_with_rand_reset.16249555106605832113318532448298586679490724962582159450877945114610554947503
    Line 279, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1479639639 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1479639639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_regwen has 3 failures.
  - 0.sram_ctrl_regwen.88070962890091153969471857625282337126009375136713131560288393913938716962623
    Line 278, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/0.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 14635395773 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xe8e05f2d
  UVM_INFO @ 14635395773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.sram_ctrl_regwen.62722242271866843946952815296804149681981879642327749896718693083465039344679
    Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/35.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 19901429820 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xcea32cf8
  UVM_INFO @ 19901429820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Offending '(((((((((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*]))))) && ((!d_mask[*]) || (d_mask[*] && (!$isunknown(d_data[(* * *)+:*])))))' has 3 failures:

Test sram_ctrl_stress_all has 3 failures.

7.sram_ctrl_stress_all.7550425007731350100576694048125094039041962624005564826258176776708606631961
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/7.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  71170033 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  71170033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.sram_ctrl_stress_all.15587040551602949039737503043454262808369013397100913405131020139970543945804
Line 277, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/34.sram_ctrl_stress_all/latest/run.log

      Offending '(((((((((!d_mask[0]) || (d_mask[0] && (!$isunknown(d_data[(8 * 0)+:8])))) && ((!d_mask[1]) || (d_mask[1] && (!$isunknown(d_data[(8 * 1)+:8]))))) && ((!d_mask[2]) || (d_mask[2] && (!$isunknown(d_data[(8 * 2)+:8]))))) && ((!d_mask[3]) || (d_mask[3] && (!$isunknown(d_data[(8 * 3)+:8]))))) && ((!d_mask[4]) || (d_mask[4] && (!$isunknown(d_data[(8 * 4)+:8]))))) && ((!d_mask[5]) || (d_mask[5] && (!$isunknown(d_data[(8 * 5)+:8]))))) && ((!d_mask[6]) || (d_mask[6] && (!$isunknown(d_data[(8 * 6)+:8]))))) && ((!d_mask[7]) || (d_mask[7] && (!$isunknown(d_data[(8 * 7)+:8])))))'
  UVM_ERROR @  50455648 ps: (tlul_assert.sv:277) [ASSERT FAILED] dDataKnown_A
  UVM_INFO @  50455648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 3 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 3 failures.
  - 27.sram_ctrl_stress_all_with_rand_reset.107221836881591544434499410398161861190729844454290841785698025169216074971084
    Line 318, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 14985989105 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x6330836a
  UVM_INFO @ 14985989105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.sram_ctrl_stress_all_with_rand_reset.20691863239290105239363000710833817150783222458529583953428330060644875538015
    Line 295, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11459090696 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe42a0380
  UVM_INFO @ 11459090696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.30228340656820449614946025739993152969774243230385617104082523434639292109046
    Line 280, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  31566368 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  31566368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.sram_ctrl_csr_mem_rw_with_rand_reset.81757870099044455584167694265697114823499226310546727299675248067456249205608
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  94952841 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  94952841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_multiple_keys has 1 failures.
  - 15.sram_ctrl_multiple_keys.23502547677927720177977856417318246528800431866196153054754185893591982626655
    Line 274, in log /container/opentitan-public/scratch/os_regression/sram_ctrl_ret-sim-vcs/15.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 10251002280 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x8c8a843b
  UVM_INFO @ 10251002280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```