SRAM_CTRL/RET Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 2.485m 2.873ms 50 50 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.720s 52.501us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.710s 21.770us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.250s 357.068us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.730s 13.657us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.650s 44.568us 18 20 90.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.710s 21.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 13.657us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 13.030s 1.531ms 50 50 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 5.940s 336.508us 50 50 100.00
V1 TOTAL 203 205 99.02
V2 multiple_keys sram_ctrl_multiple_keys 34.877m 26.017ms 50 50 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 7.037m 19.588ms 50 50 100.00
V2 bijection sram_ctrl_bijection 1.460m 20.011ms 50 50 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 24.017m 5.919ms 50 50 100.00
V2 lc_escalation sram_ctrl_lc_escalation 11.050s 10.833ms 50 50 100.00
V2 executable sram_ctrl_executable 27.401m 12.573ms 49 50 98.00
V2 partial_access sram_ctrl_partial_access 2.528m 888.083us 50 50 100.00
sram_ctrl_partial_access_b2b 10.203m 144.624ms 50 50 100.00
V2 max_throughput sram_ctrl_max_throughput 2.610m 638.017us 50 50 100.00
sram_ctrl_throughput_w_partial_write 2.477m 189.203us 50 50 100.00
V2 regwen sram_ctrl_regwen 30.737m 3.709ms 50 50 100.00
V2 ram_cfg sram_ctrl_ram_cfg 0.870s 31.336us 50 50 100.00
V2 stress_all sram_ctrl_stress_all 1.402h 71.634ms 45 50 90.00
V2 alert_test sram_ctrl_alert_test 0.720s 146.671us 50 50 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 5.490s 2.583ms 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 5.490s 2.583ms 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.720s 52.501us 5 5 100.00
sram_ctrl_csr_rw 0.710s 21.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 13.657us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 16.268us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.720s 52.501us 5 5 100.00
sram_ctrl_csr_rw 0.710s 21.770us 20 20 100.00
sram_ctrl_csr_aliasing 0.730s 13.657us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.830s 16.268us 20 20 100.00
V2 TOTAL 734 740 99.19
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 4.710s 5.130ms 20 20 100.00
V2S tl_intg_err sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
sram_ctrl_tl_intg_err 2.750s 296.361us 20 20 100.00
V2S prim_count_check sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.750s 296.361us 20 20 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 30.737m 3.709ms 50 50 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.710s 21.770us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 27.401m 12.573ms 49 50 98.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 27.401m 12.573ms 49 50 98.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 27.401m 12.573ms 49 50 98.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 11.050s 10.833ms 50 50 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 4.710s 5.130ms 20 20 100.00
V2S sec_cm_mem_readback sram_ctrl_smoke 2.485m 2.873ms 50 50 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 2.485m 2.873ms 50 50 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 2.485m 2.873ms 50 50 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 27.401m 12.573ms 49 50 98.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 11.050s 10.833ms 50 50 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 2.485m 2.873ms 50 50 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 3.180s 355.395us 5 5 100.00
V2S TOTAL 45 45 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 9.675m 5.811ms 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 1024 1040 98.46

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 16 16 14 87.50
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 99.16 94.27 99.72 100.00 95.95 99.12 97.44

Failure Buckets

Past Results