SRAM_CTRL/RET Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.099m	2.698ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	31.609s		4	5	80.00
V1	csr_rw	sram_ctrl_csr_rw	42.691s		17	20	85.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	32.746s		4	5	80.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	35.067s		4	5	80.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	45.724s		17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	42.691s		17	20	85.00
		sram_ctrl_csr_aliasing	35.067s		4	5	80.00
V1	mem_walk	sram_ctrl_mem_walk	16.500s	663.315us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.360s	183.657us	50	50	100.00
V1		TOTAL			196	205	95.61
V2	multiple_keys	sram_ctrl_multiple_keys	24.498m	78.218ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.969m	4.220ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	2.162m	10.232ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.159m	4.132ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.270s	1.010ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.076m	28.607ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.192m	267.777us	50	50	100.00
		sram_ctrl_partial_access_b2b	13.799m	91.914ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.862m	340.608us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.799m	297.392us	50	50	100.00
V2	regwen	sram_ctrl_regwen	28.216m	100.218ms	48	50	96.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.350s	139.273us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.509h	297.805ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.110s	12.934us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	42.616s		18	20	90.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	42.616s		18	20	90.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	31.609s		4	5	80.00
		sram_ctrl_csr_rw	42.691s		17	20	85.00
		sram_ctrl_csr_aliasing	35.067s		4	5	80.00
		sram_ctrl_same_csr_outstanding	41.149s		18	20	90.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	31.609s		4	5	80.00
		sram_ctrl_csr_rw	42.691s		17	20	85.00
		sram_ctrl_csr_aliasing	35.067s		4	5	80.00
		sram_ctrl_same_csr_outstanding	41.149s		18	20	90.00
V2		TOTAL			734	740	99.19
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	30.414s		19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
		sram_ctrl_tl_intg_err	42.652s		18	20	90.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	42.652s		18	20	90.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	28.216m	100.218ms	48	50	96.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	42.691s		17	20	85.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.076m	28.607ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.076m	28.607ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.076m	28.607ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.270s	1.010ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	30.414s		19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	2.099m	2.698ms	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.099m	2.698ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.099m	2.698ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.076m	28.607ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.270s	1.010ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.099m	2.698ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.650s	240.059us	5	5	100.00
V2S		TOTAL			42	45	93.33
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.695m	5.801ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			1014	1040	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	3	37.50
V2	16	16	13	81.25
V2S	3	3	1	33.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	99.13	94.27	99.72	100.00	95.81	99.12	97.44

Failure Buckets

Job returned non-zero exit code has 16 failures:

Test sram_ctrl_tl_intg_err has 2 failures.

4.sram_ctrl_tl_intg_err.24335719711107356481428068578560729506796998206527954208581259913094282414184
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_tl_intg_err/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

7.sram_ctrl_tl_intg_err.89014588876841983198106520840774653960604948831558476867457747919970910353811
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_tl_intg_err/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test sram_ctrl_csr_hw_reset has 1 failures.

4.sram_ctrl_csr_hw_reset.116364583832078219318017313025359391112203780530205422540378961597670940867
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_hw_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test sram_ctrl_csr_rw has 3 failures.

4.sram_ctrl_csr_rw.109441989142375022195070003409360614406438058011497639488219061205405768258823
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

7.sram_ctrl_csr_rw.75265891796777975591894887602846367458822835118935403578335294424866506768816
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_rw/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more failures.

Test sram_ctrl_csr_bit_bash has 1 failures.

4.sram_ctrl_csr_bit_bash.34352814232587714131345590704190365157559496894340227060156694588683003057266
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_bit_bash/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test sram_ctrl_csr_aliasing has 1 failures.

4.sram_ctrl_csr_aliasing.91227309376885323394088934761251316124452905989906939460218923195894787614445
Log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_aliasing/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Sep 18 12:49 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 4 more tests.

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 8 failures.
  - 2.sram_ctrl_stress_all_with_rand_reset.36691248544279587339621730148798118671850186788475044224889058830532988281413
    Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/2.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10889469343 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10889469343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.sram_ctrl_stress_all_with_rand_reset.37661662726811637984890628314778632476492116909455068103378020969717422507964
    Line 177, in log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/3.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2341385038 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2341385038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_regwen has 2 failures.
  - 27.sram_ctrl_regwen.22992550863211951666457789098033866566231318929395513467264392045936523263976
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/27.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 24749328556 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0xa7e58adb
  UVM_INFO @ 24749328556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.sram_ctrl_regwen.109785650322760273792992987007327450640800884357911715769560224623079485253786
    Line 109, in log /workspaces/repo/scratch/os_regression_2024_09_17/sram_ctrl_ret-sim-vcs/44.sram_ctrl_regwen/latest/run.log
```
  UVM_FATAL @ 48204304486 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x6e708025
  UVM_INFO @ 48204304486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```