SRAM_CTRL/RET Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.046m	1.476ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.060s	27.361us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.120s	14.044us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.330s	649.345us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.180s	164.444us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	19.510s	10.005ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.120s	14.044us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	164.444us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.870s	4.754ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.240s	905.610us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	29.710m	56.182ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	8.427m	4.846ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.898m	16.695ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.239m	3.642ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.490s	8.965ms	50	50	100.00
V2	executable	sram_ctrl_executable	34.389m	20.352ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.803m	248.870us	50	50	100.00
		sram_ctrl_partial_access_b2b	9.296m	21.908ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.028m	140.558us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.909m	2.429ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	29.049m	59.150ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.360s	242.488us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.858h	450.511ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.110s	14.511us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	7.660s	293.216us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	7.660s	293.216us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.060s	27.361us	5	5	100.00
		sram_ctrl_csr_rw	1.120s	14.044us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	164.444us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	198.038us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.060s	27.361us	5	5	100.00
		sram_ctrl_csr_rw	1.120s	14.044us	20	20	100.00
		sram_ctrl_csr_aliasing	1.180s	164.444us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.280s	198.038us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.070s	6.467ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
		sram_ctrl_tl_intg_err	7.020s	3.816ms	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	7.020s	3.816ms	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.049m	59.150ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	29.049m	59.150ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.120s	14.044us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.389m	20.352ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.389m	20.352ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.389m	20.352ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.490s	8.965ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.070s	6.467ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.930s	47.961us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.046m	1.476ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.046m	1.476ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.389m	20.352ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.490s	8.965ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.046m	1.476ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.770s	886.993us	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.237m	2.998ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1075	1090	98.62

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	13	81.25
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.63	99.48	96.05	99.72	100.00	97.29	99.12	98.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 9 failures.
  - 4.sram_ctrl_stress_all_with_rand_reset.45579935498664010380797379401224725821624237549563137572959481976455398334168
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1723022031 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1723022031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.sram_ctrl_stress_all_with_rand_reset.94450655565569761726037518539278929446013377532532210062092168774454477779362
    Line 328, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7935310102 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7935310102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:
- Test sram_ctrl_stress_all has 1 failures.
  - 8.sram_ctrl_stress_all.2519864029936485212773813629601431944867059324305620088525663133328099562532
    Line 251, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/8.sram_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 565564749052 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xf182d7fe
  UVM_INFO @ 565564749052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test sram_ctrl_multiple_keys has 1 failures.
  - 19.sram_ctrl_multiple_keys.9088937076783594084388490955490898601753160366649468601610647572614304332799
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/19.sram_ctrl_multiple_keys/latest/run.log
```
  UVM_FATAL @ 29072378226 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0xfa3edc2e
  UVM_INFO @ 29072378226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_tl_intg_err has 1 failures.
  - 5.sram_ctrl_tl_intg_err.56811070186823005497408542987478150742871764399193135148038893570422564618234
    Line 230, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/5.sram_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 601511436 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 601511436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (sram_ctrl_base_vseq.sv:153) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.92249980682980671627872563180431646627063555409758962829128260417449065032752
    Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10004921399 ps: (sram_ctrl_base_vseq.sv:153) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
  UVM_INFO @ 10004921399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 18.sram_ctrl_csr_mem_rw_with_rand_reset.18999235434189844054946650572352457424604949587936052204981471996253510230092
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  55514504 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  55514504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_executable has 1 failures.
  - 35.sram_ctrl_executable.77326186787140312457390477248527063250850750429153114192315550190399562998043
    Line 119, in log /workspaces/repo/scratch/os_regression_2024_10_08/sram_ctrl_ret-sim-vcs/35.sram_ctrl_executable/latest/run.log
```
  UVM_FATAL @ 118880005342 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xa5cc9970
  UVM_INFO @ 118880005342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `29d22a60a2`