SRAM_CTRL/RET Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.966m	1.269ms	49	50	98.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.050s	30.630us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.090s	17.886us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	423.419us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.090s	53.246us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.620s	180.710us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.090s	17.886us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	53.246us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	16.840s	3.268ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.110s	190.263us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	28.211m	20.442ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.826m	14.522ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.790m	14.384ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	23.620m	6.272ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.840s	3.724ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.157m	65.203ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.937m	690.122us	50	50	100.00
		sram_ctrl_partial_access_b2b	13.308m	151.896ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.986m	264.003us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.993m	446.188us	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.729m	77.888ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.310s	54.892us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.859h	18.920ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.100s	74.047us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.950s	440.863us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.950s	440.863us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.050s	30.630us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	17.886us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	53.246us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	170.504us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.050s	30.630us	5	5	100.00
		sram_ctrl_csr_rw	1.090s	17.886us	20	20	100.00
		sram_ctrl_csr_aliasing	1.090s	53.246us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.250s	170.504us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	6.270s	3.835ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
		sram_ctrl_tl_intg_err	4.570s	536.856us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.570s	536.856us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.729m	77.888ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.729m	77.888ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.090s	17.886us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.157m	65.203ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.157m	65.203ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.157m	65.203ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.840s	3.724ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	6.270s	3.835ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.966m	1.269ms	49	50	98.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.966m	1.269ms	49	50	98.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.966m	1.269ms	49	50	98.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.157m	65.203ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.840s	3.724ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.966m	1.269ms	49	50	98.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.580s	1.196ms	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	16.530m	3.770ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	6	75.00
V2	16	16	16	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.29	99.22	95.11	99.72	100.00	96.31	99.12	98.54

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 6 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 6 failures.
  - 14.sram_ctrl_stress_all_with_rand_reset.99177276187751559947861651970513766665081691660609989486542370010696065538519
    Line 210, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/14.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 709321389 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 709321389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.sram_ctrl_stress_all_with_rand_reset.47558722719420224393047133751784115184094849596642852653822032844573283878884
    Line 183, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/19.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6167661585 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6167661585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.55681362966715313632952920268135204565625698020877964427148270693030943870280
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48680200 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  48680200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.3077740919260864799070849460895121646861884573631759406494971330417154763465
    Line 93, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 395683953 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 395683953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 1 failures:
- Test sram_ctrl_smoke has 1 failures.
  - 36.sram_ctrl_smoke.57992617055282691691349041686584752026893249757552121543309443656637693639617
    Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_23/sram_ctrl_ret-sim-vcs/36.sram_ctrl_smoke/latest/run.log
```
  UVM_FATAL @ 10500321010 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x21ca2786
  UVM_INFO @ 10500321010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

SRAM_CTRL/RET Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `78ad89d1aa`