25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sram_ctrl_smoke | 2.035m | 2.868ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | sram_ctrl_csr_hw_reset | 1.020s | 36.436us | 5 | 5 | 100.00 |
| V1 | csr_rw | sram_ctrl_csr_rw | 1.050s | 21.614us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sram_ctrl_csr_bit_bash | 2.760s | 458.698us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sram_ctrl_csr_aliasing | 1.040s | 32.770us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sram_ctrl_csr_mem_rw_with_rand_reset | 3.690s | 341.583us | 18 | 20 | 90.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sram_ctrl_csr_rw | 1.050s | 21.614us | 20 | 20 | 100.00 |
| sram_ctrl_csr_aliasing | 1.040s | 32.770us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | sram_ctrl_mem_walk | 21.760s | 5.940ms | 49 | 50 | 98.00 |
| V1 | mem_partial_access | sram_ctrl_mem_partial_access | 21.698s | 49 | 50 | 98.00 | |
| V1 | TOTAL | 200 | 205 | 97.56 | |||
| V2 | multiple_keys | sram_ctrl_multiple_keys | 30.085m | 36.626ms | 50 | 50 | 100.00 |
| V2 | stress_pipeline | sram_ctrl_stress_pipeline | 7.540m | 3.692ms | 49 | 50 | 98.00 |
| V2 | bijection | sram_ctrl_bijection | 1.804m | 38.568ms | 49 | 50 | 98.00 |
| V2 | access_during_key_req | sram_ctrl_access_during_key_req | 22.464m | 13.509ms | 49 | 50 | 98.00 |
| V2 | lc_escalation | sram_ctrl_lc_escalation | 21.876s | 49 | 50 | 98.00 | |
| V2 | executable | sram_ctrl_executable | 35.714m | 220.328ms | 49 | 50 | 98.00 |
| V2 | partial_access | sram_ctrl_partial_access | 1.728m | 1.291ms | 50 | 50 | 100.00 |
| sram_ctrl_partial_access_b2b | 10.532m | 39.520ms | 50 | 50 | 100.00 | ||
| V2 | max_throughput | sram_ctrl_max_throughput | 1.874m | 194.360us | 49 | 50 | 98.00 |
| sram_ctrl_throughput_w_partial_write | 2.022m | 974.500us | 49 | 50 | 98.00 | ||
| V2 | regwen | sram_ctrl_regwen | 21.238m | 27.995ms | 47 | 50 | 94.00 |
| V2 | ram_cfg | sram_ctrl_ram_cfg | 21.765s | 49 | 50 | 98.00 | |
| V2 | stress_all | sram_ctrl_stress_all | 1.363h | 31.818ms | 49 | 50 | 98.00 |
| V2 | alert_test | sram_ctrl_alert_test | 22.965s | 49 | 50 | 98.00 | |
| V2 | tl_d_oob_addr_access | sram_ctrl_tl_errors | 7.170s | 155.654us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sram_ctrl_tl_errors | 7.170s | 155.654us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sram_ctrl_csr_hw_reset | 1.020s | 36.436us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 1.050s | 21.614us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 1.040s | 32.770us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 1.320s | 80.104us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sram_ctrl_csr_hw_reset | 1.020s | 36.436us | 5 | 5 | 100.00 |
| sram_ctrl_csr_rw | 1.050s | 21.614us | 20 | 20 | 100.00 | ||
| sram_ctrl_csr_aliasing | 1.040s | 32.770us | 5 | 5 | 100.00 | ||
| sram_ctrl_same_csr_outstanding | 1.320s | 80.104us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 727 | 740 | 98.24 | |||
| V2S | passthru_mem_tl_intg_err | sram_ctrl_passthru_mem_tl_intg_err | 6.100s | 1.511ms | 20 | 20 | 100.00 |
| V2S | tl_intg_err | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| sram_ctrl_tl_intg_err | 4.310s | 578.327us | 20 | 20 | 100.00 | ||
| V2S | prim_count_check | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | sram_ctrl_tl_intg_err | 4.310s | 578.327us | 20 | 20 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | sram_ctrl_regwen | 21.238m | 27.995ms | 47 | 50 | 94.00 |
| V2S | sec_cm_exec_config_regwen | sram_ctrl_csr_rw | 1.050s | 21.614us | 20 | 20 | 100.00 |
| V2S | sec_cm_exec_config_mubi | sram_ctrl_executable | 35.714m | 220.328ms | 49 | 50 | 98.00 |
| V2S | sec_cm_exec_intersig_mubi | sram_ctrl_executable | 35.714m | 220.328ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sram_ctrl_executable | 35.714m | 220.328ms | 49 | 50 | 98.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | sram_ctrl_lc_escalation | 21.876s | 49 | 50 | 98.00 | |
| V2S | sec_cm_mem_integrity | sram_ctrl_passthru_mem_tl_intg_err | 6.100s | 1.511ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_readback | sram_ctrl_smoke | 2.035m | 2.868ms | 49 | 50 | 98.00 |
| V2S | sec_cm_mem_scramble | sram_ctrl_smoke | 2.035m | 2.868ms | 49 | 50 | 98.00 |
| V2S | sec_cm_addr_scramble | sram_ctrl_smoke | 2.035m | 2.868ms | 49 | 50 | 98.00 |
| V2S | sec_cm_instr_bus_lc_gated | sram_ctrl_executable | 35.714m | 220.328ms | 49 | 50 | 98.00 |
| V2S | sec_cm_ram_tl_lc_gate_fsm_sparse | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| V2S | sec_cm_key_global_esc | sram_ctrl_lc_escalation | 21.876s | 49 | 50 | 98.00 | |
| V2S | sec_cm_key_local_esc | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| V2S | sec_cm_init_ctr_redun | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| V2S | sec_cm_scramble_key_sideload | sram_ctrl_smoke | 2.035m | 2.868ms | 49 | 50 | 98.00 |
| V2S | sec_cm_tlul_fifo_ctr_redun | sram_ctrl_sec_cm | 3.180s | 679.518us | 5 | 5 | 100.00 |
| V2S | TOTAL | 45 | 45 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sram_ctrl_stress_all_with_rand_reset | 8.160m | 4.328ms | 40 | 50 | 80.00 |
| V3 | TOTAL | 40 | 50 | 80.00 | |||
| TOTAL | 1012 | 1040 | 97.31 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 4 | 50.00 |
| V2 | 16 | 16 | 5 | 31.25 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.95 | 99.16 | 94.27 | 99.72 | 100.00 | 95.95 | 99.12 | 97.44 |
Job returned non-zero exit code has 15 failures:
Test sram_ctrl_max_throughput has 1 failures.
0.sram_ctrl_max_throughput.14712493361495978235494539946719785266558803921884282579348024617180272968832
Log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_max_throughput/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 08:40 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sram_ctrl_throughput_w_partial_write has 1 failures.
0.sram_ctrl_throughput_w_partial_write.40909673674869651987033285794067407869636225999375234256167051096722865066340
Log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_throughput_w_partial_write/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 08:40 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sram_ctrl_lc_escalation has 1 failures.
0.sram_ctrl_lc_escalation.4583440012355522772600549796468281939108817294933846036586230096871115262723
Log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_lc_escalation/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 08:40 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sram_ctrl_access_during_key_req has 1 failures.
0.sram_ctrl_access_during_key_req.30120548532861938085493811813742868471202318310743428583277782333912059215865
Log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_access_during_key_req/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 08:40 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sram_ctrl_executable has 1 failures.
0.sram_ctrl_executable.54032410716962448402116547482285613651599939449316279854467436617544037124167
Log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/0.sram_ctrl_executable/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 11 08:40 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 10 more tests.
UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
9.sram_ctrl_stress_all_with_rand_reset.64984025192507335815740271057928015196174652428856144294682481937009468679362
Line 230, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/9.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1302951855 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1302951855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.sram_ctrl_stress_all_with_rand_reset.26821215375300066629680476242103095577227818793670584347990173775685780421884
Line 106, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1072831394 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1072831394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=* has 2 failures:
3.sram_ctrl_regwen.106542318551934672247238071835034741010539718721844312440979235557556165469176
Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/3.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 20295360918 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x299b1967
UVM_INFO @ 20295360918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.sram_ctrl_regwen.47485251174772016656791883406860617914071294586633088346500912915156137072205
Line 105, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/14.sram_ctrl_regwen/latest/run.log
UVM_FATAL @ 68978624765 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_regwen_vseq] Timeout waiting tl_access : addr=0x7c040fa0
UVM_INFO @ 68978624765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
8.sram_ctrl_csr_mem_rw_with_rand_reset.83215500717726060737114805323508613961320865974550755214817080632467645190530
Line 87, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 233158795 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
UVM_INFO @ 233158795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
13.sram_ctrl_csr_mem_rw_with_rand_reset.58284109392588624158768188913082751915569098738226764082793189204757391262620
Line 86, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 25588625 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
UVM_INFO @ 25588625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
27.sram_ctrl_stress_all_with_rand_reset.42424820553611397056350924999370273454905461637388455731063974729313524340104
Line 253, in log /workspaces/repo/scratch/os_regression_2024_09_10/sram_ctrl_ret-sim-vcs/27.sram_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 213615885 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 213615885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---