SRAM_CTRL/RET Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.619m	108.905us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.010s	77.645us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	28.421us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.300s	123.170us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.020s	22.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.860s	476.000us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	28.421us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	22.189us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	19.410s	6.324ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	10.050s	192.673us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	43.424m	22.291ms	49	50	98.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	9.700m	21.067ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	2.075m	53.975ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	25.944m	10.766ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.440s	2.355ms	50	50	100.00
V2	executable	sram_ctrl_executable	39.937m	21.958ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.960m	208.300us	50	50	100.00
		sram_ctrl_partial_access_b2b	12.462m	50.232ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.959m	146.481us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.834m	183.845us	50	50	100.00
V2	regwen	sram_ctrl_regwen	31.368m	16.260ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.510s	53.517us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.604h	80.834ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.180s	16.787us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.630s	2.896ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.630s	2.896ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.010s	77.645us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	28.421us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	22.189us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	74.462us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.010s	77.645us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	28.421us	20	20	100.00
		sram_ctrl_csr_aliasing	1.020s	22.189us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	74.462us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.330s	2.706ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
		sram_ctrl_tl_intg_err	3.450s	1.568ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.450s	1.568ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	31.368m	16.260ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	31.368m	16.260ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	28.421us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	39.937m	21.958ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	39.937m	21.958ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	39.937m	21.958ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.440s	2.355ms	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.330s	2.706ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_smoke	1.619m	108.905us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.619m	108.905us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.619m	108.905us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	39.937m	21.958ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.440s	2.355ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.619m	108.905us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.940s	636.123us	5	5	100.00
V2S		TOTAL			45	45	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.953m	2.198ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			1031	1040	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.22	95.11	99.72	100.00	96.31	99.12	98.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 5 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 5 failures.

    • 4.sram_ctrl_stress_all_with_rand_reset.2357755042272423149047721951231430886634303840996379282735067965045789766668
      Line 92, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/4.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2723091442 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2723091442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.sram_ctrl_stress_all_with_rand_reset.84450720282434397404647861620520109019460728134464070972142869354030268065954
      Line 158, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2956027241 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2956027241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_stress_all has 1 failures.

    • 32.sram_ctrl_stress_all.52704734330619637072893992104682174024096550121027040070326913934221240900435
      Line 117, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/32.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 164524877244 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x82d93a7b
        UVM_INFO @ 164524877244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sram_ctrl_multiple_keys has 1 failures.

    • 47.sram_ctrl_multiple_keys.96865686073148595450709683290654020287707191331859743963329317732464559530687
      Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/47.sram_ctrl_multiple_keys/latest/run.log

        UVM_FATAL @ 24851893698 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_multiple_keys_vseq] Timeout waiting tl_access : addr=0x7983d23c
        UVM_INFO @ 24851893698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 1.sram_ctrl_csr_mem_rw_with_rand_reset.65428665290679329849873549293647855600338807521907938382098067190902932723099
      Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  39698197 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  39698197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 9.sram_ctrl_csr_mem_rw_with_rand_reset.23172844190046374824931039448825238591989805774985434565787374834010648307089
      Line 87, in log /workspaces/repo/scratch/os_regression_2024_10_02/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 164710390 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
        UVM_INFO @ 164710390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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