SRAM_CTRL/RET Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.724m	738.932us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.030s	44.362us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.080s	18.451us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.520s	44.864us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.230s	20.305us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.590s	80.525us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.080s	18.451us	20	20	100.00
		sram_ctrl_csr_aliasing	1.230s	20.305us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	17.290s	4.348ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	9.290s	1.190ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	35.330m	37.564ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.976m	21.485ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.908m	4.876ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	24.959m	5.082ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	17.320s	962.983us	50	50	100.00
V2	executable	sram_ctrl_executable	34.313m	65.574ms	49	50	98.00
V2	partial_access	sram_ctrl_partial_access	1.810m	244.929us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.745m	25.152ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.770m	146.729us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.753m	433.302us	50	50	100.00
V2	regwen	sram_ctrl_regwen	26.914m	121.782ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.320s	29.858us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.507h	135.247ms	49	50	98.00
V2	alert_test	sram_ctrl_alert_test	1.090s	14.334us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	8.360s	159.138us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	8.360s	159.138us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.030s	44.362us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	18.451us	20	20	100.00
		sram_ctrl_csr_aliasing	1.230s	20.305us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.230s	35.876us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.030s	44.362us	5	5	100.00
		sram_ctrl_csr_rw	1.080s	18.451us	20	20	100.00
		sram_ctrl_csr_aliasing	1.230s	20.305us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.230s	35.876us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	7.130s	731.790us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
		sram_ctrl_tl_intg_err	5.350s	769.174us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.350s	769.174us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	26.914m	121.782ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	26.914m	121.782ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.080s	18.451us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	34.313m	65.574ms	49	50	98.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	34.313m	65.574ms	49	50	98.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	34.313m	65.574ms	49	50	98.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	17.320s	962.983us	50	50	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	7.130s	731.790us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.960s	74.764us	50	50	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.724m	738.932us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.724m	738.932us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	34.313m	65.574ms	49	50	98.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	17.320s	962.983us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.724m	738.932us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	5.780s	377.220us	5	5	100.00
V2S		TOTAL			95	95	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.118m	6.125ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			1082	1090	99.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	16	16	14	87.50
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.63	99.48	96.05	99.72	100.00	97.29	99.12	98.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 4 failures.

    • 10.sram_ctrl_stress_all_with_rand_reset.10540223103979045427014284760940908373871582132517980676913311862788997180520
      Line 91, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/10.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1597771424 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1597771424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 20.sram_ctrl_stress_all_with_rand_reset.2277252112861152693809810545192997525888827704585209368027406106390119791386
      Line 248, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/20.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4259084601 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 50000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4259084601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL (cip_base_vseq.sv:268) [sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=* has 2 failures:

  • Test sram_ctrl_executable has 1 failures.

    • 5.sram_ctrl_executable.68451132863315565112815364947438085922900854372813264943495551177823759803809
      Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/5.sram_ctrl_executable/latest/run.log

        UVM_FATAL @ 16606249256 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0x47c52810
        UVM_INFO @ 16606249256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sram_ctrl_stress_all has 1 failures.

    • 6.sram_ctrl_stress_all.83296032552051315165160703712075759804880675828521915774730313671271451932844
      Line 99, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 29773009651 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.sram_ctrl_executable_vseq] Timeout waiting tl_access : addr=0xc68ba54b
        UVM_INFO @ 29773009651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 2.sram_ctrl_csr_mem_rw_with_rand_reset.59912698444960931304602909834096543454546303672202141929921200074788643414336
      Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  33822991 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
        UVM_INFO @  33822991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 19.sram_ctrl_csr_mem_rw_with_rand_reset.52293143627612048724760930810530942690335851680248730148257691040346953453916
      Line 93, in log /workspaces/repo/scratch/os_regression_2024_10_11/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  61110768 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @  61110768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2024.10.10_10.19.11
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• 2024.09.19_09.08.42
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