Unified Coverage Report :: Module :: sysrst_ctrl_ulp

Module : sysrst_ctrl_ulp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_ulp	0.00	0.00	0.00

---

Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
31.55	0.00	0.00	94.65				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect_ac_present	0.00	0.00	0.00		0.00	0.00
u_sysrst_ctrl_detect_lid_open	0.00	0.00	0.00		0.00	0.00
u_sysrst_ctrl_detect_pwrb	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_ulp

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
CONT_ASSIGN	89	1	0	0.00
CONT_ASSIGN	93	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
89	0	1
93	0	1

---

Cond Coverage for Module : sysrst_ctrl_ulp

	Total	Covered	Percent
Conditions	8	0	0.00
Logical	8	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       93
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered