Unified Coverage Report :: Module :: sysrst_ctrl

Module : sysrst_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
31.55	0.00	0.00	94.65

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	31.55	0.00	0.00	94.65

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
31.55	0.00	0.00	94.65

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
67.80	72.20	71.99	87.44	0.00	75.49	99.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
sysrst_ctrl_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_prim_flop_2sync_input	0.00	0.00				0.00
u_reg	94.53	99.18	94.00	81.33		98.84	99.30
u_sysrst_ctrl_autoblock	0.00	0.00	0.00		0.00	0.00
u_sysrst_ctrl_combo	0.00	0.00	0.00		0.00	0.00
u_sysrst_ctrl_intr	0.00	0.00	0.00			0.00
u_sysrst_ctrl_keyintr	0.00	0.00	0.00		0.00	0.00
u_sysrst_ctrl_pin	0.00	0.00	0.00			0.00
u_sysrst_ctrl_ulp	0.00	0.00	0.00		0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl

	Line No.	Total	Covered	Percent
TOTAL		17	0	0.00
CONT_ASSIGN	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	107	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
CONT_ASSIGN	109	1	0	0.00
CONT_ASSIGN	110	1	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	113	1	0	0.00
CONT_ASSIGN	114	1	0	0.00
CONT_ASSIGN	303	1	0	0.00
CONT_ASSIGN	304	1	0	0.00
CONT_ASSIGN	305	1	0	0.00
CONT_ASSIGN	306	1	0	0.00
CONT_ASSIGN	307	1	0	0.00
CONT_ASSIGN	308	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	311	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1
107	0	1
108	0	1
109	0	1
110	0	1
111	0	1
113	0	1
114	0	1
303	0	1
304	0	1
305	0	1
306	0	1
307	0	1
308	0	1
310	0	1
311	0	1

---

Cond Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Conditions	51	0	0.00
Logical	51	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       68
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       106
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       107
 EXPRESSION (reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       108
 EXPRESSION (reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       109
 EXPRESSION (reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i)
             ---------------1---------------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       110
 EXPRESSION (reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i)
             -----------------1----------------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       111
 EXPRESSION (reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i)
             ----------------1---------------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       303
 EXPRESSION (reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       305
 EXPRESSION (reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       306
 EXPRESSION (reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int)
             ----------------1---------------   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       307
 EXPRESSION (reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int)
             -----------------1-----------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       308
 EXPRESSION (reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int)
             ----------------1----------------   ----------2----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : sysrst_ctrl

	Total	Covered	Percent
Totals	47	37	78.72
Total Bits	374	354	94.65
Total Bits 0->1	187	177	94.65
Total Bits 1->0	187	177	94.65

Ports	47	37	78.72
Port Bits	374	354	94.65
Port Bits 0->1	187	177	94.65
Port Bits 1->0	187	177	94.65

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T6,T7	Yes	T2,T6,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T2,T6,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T4,T7	Yes	T2,T4,T7	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
wkup_req_o	No	No		No		OUTPUT
rst_req_o	No	No		No		OUTPUT
intr_event_detected_o	Yes	Yes	T8,T9,T10	Yes	T8,T9,T10	OUTPUT
cio_ac_present_i	No	No		No		INPUT
cio_ec_rst_l_i	No	No		No		INPUT
cio_key0_in_i	No	No		No		INPUT
cio_key1_in_i	No	No		No		INPUT
cio_key2_in_i	No	No		No		INPUT
cio_pwrb_in_i	No	No		No		INPUT
cio_lid_open_i	No	No		No		INPUT
cio_flash_wp_l_i	No	No		No		INPUT
cio_bat_disable_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_flash_wp_l_o	Yes	Yes	T1,T5,T11	Yes	T1,T5,T11	OUTPUT
cio_ec_rst_l_o	Yes	Yes	T5,T12,T13	Yes	T5,T12,T13	OUTPUT
cio_key0_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_key1_out_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_key2_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_pwrb_out_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cio_z3_wakeup_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
cio_bat_disable_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_flash_wp_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ec_rst_l_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key0_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key1_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_key2_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pwrb_out_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_z3_wakeup_en_o	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range